氧化鉿電阻式記憶體可靠度之研究

此篇論文之目的為研究與改善氧化鉿電阻式記憶體的電阻轉換特性可靠度，雖然3 nm氧化鉿元件不需要生成過程且展現足夠的高低電阻比值與不錯的記憶體特性，然而，由於此種元件不夠高的高阻態使其無法降低操作電流，顯示3 nm氧化鉿不適合電阻式記憶體未來發展。電流暴衝會降低高阻態之阻值以及提高操作電流，是元件操作過程中最大的問題，可藉由電晶體來有效控制限流，所以10 nm氧化鉿1T1R元件展現超過1 Mohm之高阻態、超過100之高低電阻比值與高達1010次的操作次數。除了單元元件，我們更研究1kb陣列之操作可靠度，在100 μA操作電流下1kb陣列可被操作達106次，以新穎寫入驗證機制可有效抑制軟錯誤，且在操作過程中能夠集中高低阻態的分布以及增加高低電阻比值，此外，我們提出針對低阻態的新穎SRS驗證機制可能物理模型。對於奈米級元件，我們開發了concave與pillar結構並研究其電阻轉換的行為，在concave結構，30 nm的1T1R元件成功被製作且展現基本的特性，但concave在結構上有電流暴衝的問題以致元件特性無法被改善，必須使用pillar元件來解決結構上電流暴衝的問題，50 nm的pillar元件成功被製作，以不具與Ti反應的氮化矽為覆蓋層能夠有效提升其操作特性，如：與深微米元件相當的高阻態、200 °C的熱穩定性以及良好的操作可靠度。由此可知，氧化鉿電阻式記憶體具有優異的操作次數達1010、在1kb陣列有很高的元件良率與相當大的高低電阻比值、以及可縮小至30 nm的微縮性，加上低操作功耗以及高速操作，使氧化鉿電阻式記憶體能夠有取代動態隨機存取與快閃記憶體，成為下世代的非揮發性記憶體的潛力。

關鍵字

氧化鉿；電阻式記憶體；可靠度

並列摘要

The motivation of this thesis is to study and to improve the switching reliability of the HfOX resistive memory. Although the forming-free device with a 3-nm-thick HfOX film exhibits large on/off resistance ratio and good memory performances, the RHIGH of the forming-free device is not high enough to guarantee lower the operation current. Current overshoot, which degrades the RHIGH and elevating the operation current, is a critical issue for the operation of resistive memory and can be solved by using the transistor to perfectly clamp the current. The high RHIGH over 1 Mohm, large on/off ratio of 100, and excellent endurance of 1010 cycles is demonstrated for the 10-nm-thick HfOX device with 1T1R architecture. Under the appropriate current of 100 μA, the 1kb memory array exhibits the endurance exceeding more than 106 cycles. The effective suppression of soft-errors by novel verification methods can tighten RHIGH and RLOW distributions and restore the on/off ratio of the 1kb array during the endurance test. A possible scenario for the novel high voltage SET-RESET-SET (SRS) verification of low resistance state is addressed. Two nanometer scale devices with the concave and pillar structure are fabricated and investigated for the resistive switching. The 30 nm 1T1R device with adequate resistive switching performances is demonstrated in the concave structure. By using a Si3N4 encapsulation layer which is inert to Ti capping layer, the 50 nm pillar device exhibits a high RHIGH closing to that of micrometer scale control device, robust thermal immunity at 200 °C, good cycling reliability, and no current overshoot problem. Owing to excellent switching endurance of 1010 cycles, high device yield and large on/off ratio in the 1kb array, and superior scalability to 30 nm, the HfOX resistive memory with low operation power and ultra-high switching speed has a strong potential for replacing DRAM and flash, and being the next generation non-volatile memory.

並列關鍵字

HfOx ； RRAM ； reliability

參考文獻

[72] M. J. Kim, I. G. Baek, Y. H. Ha, S. J. Baik, J. H. Kim, D. J. Seong, S. J. Kim, Y. H. Kwon, C. R. Lim, H. K. Park, D. Gilmer, P. Kirsch, R. Jammy, Y. G. Shin, S. Choi, and C. Chung, “Low power operation bipolar TMO ReRAM for sub 10 nm era,” in IEDM Tech. Dig., pp. 444-447, 2010.

[59] S. S. Sheu, P. C. Chiang, W. P. Lin, H. Y. Lee, P. S. Chen, Y. S. Chen, T. Y. Wu, F. T. Chen, K. L. Su, M J. Kao, K. H. Cheng, M.-J. Tsai, “A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme,” Symp. On VLSI Circuit, pp. 82-83, 2009.

[18] Y. S. Chen, H. Y. Lee, P. S. Chen, P. Y. Gu, C. W. Chen, W. P. Lin, W. H. Liu, Y. Y. Hsu, S. S. Sheu, P. C. Chiang, W. S. Chen, F. T. Chen, C. H. Lien, and M.-J. Tsai, “Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity,” in IEDM Tech. Dig., pp. 105-108, 2009.

[64] B. Chen, Y. Lu, B. Gao, Y. H. Fu, F. F. Zhang, P. Huang, Y. S. Chen, L. F. Liu, X. Y. Liu, J. F. Kang, Y. Y. Wang, Z. Fang, H. Y. Yu, X. Li, X. P. Wang, N. Singh, G. Q. Lo, and D. L. Kwong, “Physical mechanism of endurance degradation in TMO-RRAM,” in IEDM Tech. Dig., pp. 283-286, 2011.

[75] W. C. Chien, M. H. Lee, F. M. Lee, Y. Y. Lin, H. L. Lung, K. Y. Hsieh, and C. Y. Lu, “A multi-level 40nm WOX resistive memory with excellent reliability,” in IEDM Tech. Dig., pp. 725-728, 2011.

國際替代計量

氧化鉿電阻式記憶體可靠度之研究

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