低功率嵌入式處理器之編譯器最佳化研究

Compiler Optimizations on Embedded Processors for Low Power

游逸平(Yi-Ping You)

指導教授 ： 李政崑

國立清華大學/電機資訊學院/資訊工程學系/博士(2007年)

摘要

現今，有限電力之移動式及嵌入式運算應用相當普遍。因為這些系統受限於有限的電池壽命，因此電力消耗成為系統設計的主要考量因素；換言之，減少耗能是現今軟、硬體開發者重大的挑戰之一。一般而言，在互補金屬氧化物導體電路中，邏輯閘主要的電能消耗是在轉換活動時（當邏輯閘的輸出從 0 變成 1、或從 1 變成 0）發生，但隨著半導體製程技術的演進（電晶體的大小愈來愈小），漏電消耗占全部耗能的比例也愈來愈高。過去，減少處理器耗電或耗能的問題已經在實體線路、邏輯、電路等層面被廣泛地探討與研究，而現今，該問題仍是許多電腦組織架構與系統軟體設計研究的熱門議題。

在本論文中，我們將介紹兩項利用系統軟體技術達成降低耗能的研究：其一、運用編譯器技術之安插指令到程式中來關閉與開啟功能元件，以降低漏電能源的消耗。亦即，當某一個功能元件呈現「閒置」狀態時便產生電源控制指令，且能有效地擺放這些指令使得安插的指令數最少。其二、單一處理器、或多處理器，甚至是多電源域處理器中作業系統內即時排程的問題，且該處理器具有調整運作電壓及關閉電源之功能。

實驗模擬結果顯示這兩項研究方法都能有效減少耗能。進一步而言，利用編譯器產生電源閘控控制的方法相對於未使用電源閘控機制的方法，平均而言大約能減少百分之十一點九的處理器整體耗能（包括動態耗能與漏電耗能等），但程式碼大小大約增加百分之二十五，效能大約降低不到百分之一；另一個使用動態電壓調整的即時排程方法相對未使用動態電壓調整機制的方法，實驗結果顯示在三個真實應用程式（CNC、GAP、以及videophone）的正規化耗能分別為百分之五十三點七四、百分之三十七點八一，以及百分之十三點一零，並且當我們將此方法應用到一個特定的安全處理器上時，對於該處理器上的 AES 模組與 RSA 模組則分別可降低約百分之四十五及百分之二十的電源消耗。

關鍵字

嵌入式處理器 ； 低功率編譯器 ； 低功率作業系統 ； 漏電消耗 ； 電源閘控 ； 可變電壓排程

並列摘要

The popularity of power-constrained mobile and embedded computing applications is increasing rapidly. For such systems, power consumption is a key consideration to design goals because of the limited battery lifetime, and reducing power consumption represents a crucial challenge for today's software and hardware developers. In CMOS circuits, power is mainly dissipated in a gate during transitional activities --- when the gate output transits from 0 to 1 or from 1 to 0, but leakage power is representing a greater proportion of total power dissipation as the feature size of semiconductor technology continues to reduce. The problem of reducing processor power/energy consumption has been studied at physical-, logic-, and circuit-level extensively before, and now it is actively studied by architects and system software designers.

In this thesis we will present investigations on how system software techniques can be used to minimize energy consumption. This includes two approaches: one emphasizes compilation techniques to insert instructions into programs to shut down and wake up function units as appropriate (i.e., not only to generate power-control instructions whenever a function unit goes `idle', but to produce a proper placement for power-control instructions so as to reduce the amount of such instructions) in order to reduce leakage energy consumption, and the other focuses on real-time scheduling problems in operating systems on a single processor (or multiple processors) with the ability to scale their operating supply voltages or even on processors with multiple voltage domains. Simulations demonstrate the effectiveness of these two methodologies. Specifically, the approach using compilers to generate power-gating controls reduces the overall energy consumption, including both dynamic and leakage energy consumption, of a processor by average of 11.9% compared with the one without power-gating mechanism, while the code size growth in terms of the amount of total instructions and the performance degradation are 25% and less than 1% on average, respectively. In the other approach that involves a real-time scheduling with variable supply voltages, the average normalized energy consumption of three real-world applications (CNC, GAP, and videophone) under an eight-voltage-level system is 53.74%, 37.81%, and 13.10%, respectively. Moreover, it has averages of 45% and 20% reduction of AES and RSA modules compared with an ordinary scheduler without energy consideration, respectively, when applying the approach on a specific security processor. We also address the potential issues when combining both compiler and operating system techniques for power management.

並列關鍵字

Embedded Processors ； Power-Aware Compilers ； Power-Aware Operating Systems ； Leakage Power Dissipation ； Power Gating ； DVS Scheduling

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