Title

展頻時脈產生器

Translated Titles

Spread Spectrum Clock Generator

Authors

洪仕哲

Key Words

展頻時脈產生器 ; 鎖相迴路 ; 電磁干擾 ; 三角積分調變 ; EMI ; PLL ; SSCG

PublicationName

清華大學電機工程學系所學位論文

Volume or Term/Year and Month of Publication

2013年

Academic Degree Category

碩士

Advisor

張慶元;黃錫瑜

Content Language

繁體中文

Chinese Abstract

電腦資料傳輸介面(SATA)近來已成為資料儲存硬碟間重要的傳輸介面,隨著傳輸時脈越快,電磁干擾(EMI)的問題日益嚴重。借由濾波、屏蔽與展頻時脈可抑制電磁干擾的程度。使用濾波與屏蔽技術會增加重量與面積,並不適用於可攜帶式產品中,因此基於調頻方式的展頻時脈技術為最簡單且有效的方法。展頻時脈技術在時脈中心頻率以調頻的方式,將集中在中心頻率的能量分散至頻譜上。展頻時脈可將時脈中的基頻與高次諧波項對系統所造成的電磁干擾降低。 本論文使用ΔΣ分數型頻率合成器,結合一無須額外時脈的數位三角波型產生器與半除數除頻器,實現一應用於Serial-ATA II 的展頻時脈產生器。本論文實現的半除數除頻器的方法,只需在傳統的可程式化整數除頻器外,額外加入一負緣觸發正反器以及相位結合電路即可,因此無須增加太多的功耗。由於半除數除頻器在ΔΣ調變器工作時具有較小的相位跳動,因此可抑制ΔΣ調變器所產生的量化雜訊。 本論文所實現的展頻時脈產生器使用台灣積體電路公司0.18µm 1P6M CMOS 製程設計與佈局,中心操作頻率為3GHz借由頻率30 KHz的內建三角波型產生器可達到下展4883ppm的展頻範圍。在3GHz展頻的情況下時脈產生器rms 抖動量為6.65ps,展頻後rms抖動量為6.94ps,展頻後對電磁干擾的抑制量約為13dB。展頻時脈產生器在1.8-V電壓操作下功率消耗為12mW,整體晶片面積為1090×1330µm^2。

English Abstract

The serial advanced technology attachment (SATA) is becoming an important technique for internal storage interconnection. As the clock becomes faster, the electromagnetic interference (EMI) issue is harmful. The level of EMI can be mitigated with the help of filters, shielding and spread spectrum clocking. Spread spectrum clocking technique, based on a frequency modulation, has been the simplest and effective way. The frequency modulation alters the center frequency of the clock and spreads the power of spectrum over a broader range. This approach reduces the fundamental clock frequency EMI, as well as the harmonic components of higher order, decreasing the EMI radiation of whole system. A Spread Spectrum Clock Generator (SSCG) for Serial-ATA II is realized in this thesis by a delta-sigma fractional-N frequency synthesizer with a digital triangular profile generator without external clock and a half-integer divider. By adding only a negative-edge-triggered resampler and using phase combination technique, the half-integer divider can be realized by any kind of integer programmable divider with little power consumption added. This Half-integer divider utilized a half division ration to have a small phase jump to reduce quantization noise. The SSCG achieves an output clock of 3 GHz and 4883ppm down spread with a 30 KHz triangular waveform and been designed based on TSMC 0.18µm 1P6M CMOS process. The rms jitter of spread-spectrum clock is 6.94ps.The EMI reduction is 13dB.The power is 12mW under 1.8-V.The chip area is 1090×1330µm^2.

Topic Category 電機資訊學院 > 電機工程學系所
工程學 > 電機工程
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