Fast-Lock Tri-State Phase-Locked Loop Using Dual-Edge Triggered PFD and Bandwidth Controller

使用雙緣觸發相位頻率偵測器與頻寬控制器之快速鎖定三種狀態鎖相迴路

邵弼煌(Pi-Huang Shao)

指導教授 ： 張慶元

國立清華大學/電機資訊學院/電機工程學系/碩士(2010年)

摘要

A fast-lock tri-state phase-locked loop (PLL) using the dual-edge triggered phase frequency detector (PFD) and the bandwidth controller is presented. The proposed PLL uses the tri-state bandwidth design to achieve fast locking and attain better output jitter performance. If the PLL is out of lock, it will operate in a wide-bandwidth (fractional-N state) to achieve fast tracking during transient. Next, the PLL will be in a middle-bandwidth (integer-N state) to eliminate the fractional spur, if the phase error between reference clock and feedback signal is limited to π/10. Finally, the PLL is in a narrow-bandwidth (small charge pump current state) to attain the lower jitter on the output frequency during stable state. Moreover, this thesis generalizes a variable-bandwidth scheme, introducing a PLL that changes the bandwidth not only by switching the divider ratio but also by switching the charge pump current.
Compared with traditional PFDs, the proposed dual-edge triggered PFD rapidly reduces the phase error between reference clock and feedback signal during transient time to achieve fast tracking. In addition, the bandwidth controller automatically detects the PLL’s locking status to switch its bandwidth state without costing a large area. The PLL is implemented under TSMC 0.18μm 1P6M CMOS process and the supply voltage is 1.8V. The post-simulation shows that the locking time of the proposed PLL can be reduced over 73% in comparison to the conventional PLL.

關鍵字

鎖相迴路 ； 相位頻率偵測器 ； 快速鎖定

並列摘要

本論文提出，使用雙緣觸發相位頻率偵測器與頻寬控制器之快速鎖定三種狀態鎖相迴路。本論文所提出的鎖相迴路，利用三種頻寬狀態流程達到快速鎖定以及低相位抖動效果。如果鎖相迴路為脫鎖狀態，則在暫態時鎖相迴路操作在大頻寬狀態(非整數模式)達到快速鎖定；接著，當參考時脈訊號與回授訊號間的相位差小於 π/10 時，則鎖相迴路操作在中頻寬狀態(整數模式)，使得消除小指數突波；最後穩定時，鎖相迴路操作在小頻寬狀態(小電荷幫浦電流)，使得頻率輸出端得到較小的相位抖動。本論文提出新的可適應性頻寬架構，除了可藉由改變電荷幫浦電流大小達到頻寬的調整，也可藉由調整除頻數的大小達到頻寬的調整。
相較於傳統的相位頻率偵測器，本文所提出的雙緣觸發相位頻率偵測器能快速地減小參考時脈與回授訊號間的相位差，以達到快速鎖定。此外，本文提出的頻寬控制器能自動偵測鎖相迴路的鎖定狀態，在不消耗過大面積的情況下達到迴路頻寬的自動切換。本文所提出的鎖相迴路使用TSMC 0.18μm 1P6M CMOS process完成晶片，供應電壓為1.8V，佈局後的模擬結果相較於傳統的鎖相迴路，本文所提出的鎖相迴路能有效地減少鎖定時間，改善的鎖定時間為73%。

並列關鍵字

PLL ； PFD ； fast-lock

參考文獻

[12] W. H. Chiu, Y. H. Huang, and T. H. Lin, “A 5GHz phase-locked loop using dynamic phase-error compensation technique for fast settling in 0.18um CMOS,” Proc. of Symposium on VLSI Circuits, pp. 128-129, 2009.

[1] K. Woo, Y. Liu, E. Nam, and D. Ham, “Fast-Lock Hybrid PLL Combining Fractional- N and Integer-N Modes of Differing Bandwidths,” IEEE Journal of Solid-State Circuits, vol. 43, no. 2, pp. 379-389, 2008.

[2] C. Y. Yang, and S. I. Liu, “Fast-switching frequency synthesizer with a discriminator-aided phase detector,” IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp. 1445-1452, 2000.

[3] K. H. Cheng, W. B. Yang, and C. M. Ying, “A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop,” IEEE Transactions on Circuits and Systems II, vol. 50, no. 11, pp. 892-896, 2003.

[4] J. Hakkinen, and J. Kostamovaara, “Speeding up an integer-N PLL by controlling the loop filter charge,” IEEE Transactions on Circuits and Systems II, vol. 50, no. 7, pp. 343-354, 2003.