雙指令執行之超長指令集架構數位訊號處理器之設計與驗證

Design and Verification for Dual Issue VLIW Digital Signal Processor

陳志強(Chih-Chiang Chen)

指導教授 ： 張世杰

國立清華大學/電機資訊學院/資訊工程學系/碩士(2008年)

https://doi.org/10.6843/NTHU.2008.00641

摘要

數位訊號處理器被廣泛用於處理多媒體的運算, 例如聲音,影像,或者數位訊號處理的演算法。但是隨著資料量的增加,必須在相同的時間內處理更大量的資料,因此數位訊號處理器的效能為最重要的因素。而指令階層的平行化是一種最直接可以增加效能的方法。但是編譯器所產生的群組化的指令必須使用大量的記憶體空間，因此在我們的論文中，我們提出一種特殊的結構，動態式指令群組化硬體加速，不大量增加記憶體空間的情況下利用硬體在執行的時後去找出更多的獨立的指令群組進而增加 指令階層的平行化，並且由實驗結果發現此硬體加速器可以增加效能3%~6%左右。

關鍵字

數位訊號處理器 ； 超長指令集 ； 雙指令執行

並列摘要

Digital Signal Processors (DSP) have been widely used in processing video and audio streaming data. Due to the increasing number of streaming data, increasing throughput is the key issue in designing DSP architecture. One way to increase the throughput of DSP is to increase the instruction level parallelism. To increase the instruction level parallelism, many architectures are proposed and can be classified into two main approaches, the superscaler and the VLIW architectures. Among the hardware architectures, the VLIW attracts a lot attention due to its simple hardware complixity. However, the VLIW architecture suffers from the problem of memory explosion due to the overhead of instruction grouping. To improve the problem of memory explosion, we propose a novel DSP architecture which contains three pipelines and performs dynamic instruction grouping by hardware. The experimental results shows that our architecture can reduce 6% of memory requiremnt on average and still achieve 2% of performance improvement.

並列關鍵字

EPIC ； VLIW ； dual issue

參考文獻

[1] M.S. Schlansker and B.R. Rau,”EPIC: Explicitly Parallel Instruction Computing” Computer, 2000, pp. 37-45.

[5] H. Sharangpani, K. Arora, “Itanium Processor Microarchitecture,” IEEE Micro, 2000, pp. 24-43.

[6] R.K. Kolagotla, et al., “A 333-MHz dual-MAC DSP architecture for next-generation wireless applications,” in Proc. IEEE Int. Conf. Acoustics, Speech, and Signal Processing, vol. 2, May 2001, pp. 1013-1016.

[7] R.K. Kolagotla, et al., “High Performance Dual-MAC DSP Architecture,” IEEE Signal Processing Magazine, vol. 19, 2002, pp. 42–53.

[8] D. Pham, et al., "The Design and Implementation of a First-Generation CELL Processor", 10.2 Proc. of ISSCC 2005.