以FPGA實現倒傳遞類神經網路並應用於肌電圖分類

EMG Classification using Artificial Neural Network Implement on FPGA

田榮雯(Rong-Wen Tien)

指導教授 ： 徐良育

中原大學/工學院/醫學工程研究所/碩士(2001年)

https://doi.org/10.6840/cycu200100149

摘要

語言為人類溝通、表達思想最重要的能力。通常失去語言能力的人，簡稱聽障人士，皆因聽覺系統或發音系統發生障礙造成。在日常生活上，聽障人士僅能運用手語、唇語，或是利用紙筆作為溝通的工具。當聽障人士與正常人溝通時，便無法細膩的表現語意。至今，針對聽障人士仍無一個有效的輔具來改善溝通上的不便。另一方面，在臨床病理研究中，肌電訊號已廣泛應用在診斷肌肉性、神經性病變及設計控制義肢手部動作等；義肢控制的設計上，主要以類神經網路作為肌電訊號辨識處理的主要核心。因此，建構一可攜式的肌電訊號/語音轉換系統，消除聽障人士溝通上的困難，為本研究主要的動機。而研究的架構上，將以硬體電路實現辨識手語的類神經網路。
本研究的目的，是以倒傳遞神經網路作為肌電訊號(EMG)辨識系統的主軸，並實現在FPGA晶片上。研究中，先以Matlab軟體作為軟體程式驗證的環境，依據基本倒傳遞網路演算法並自行發展之General Back-propagation Neural Network(GBPN)網路，利用負梯度學習法則來完成學習效果。搭配本實驗室研發之七通道肌電訊號擷取系統，擷取手前臂肌電訊號，透過六種基本特徵植萃取處理，經正規化後送入神經網路作實際應用的模擬與測試。對照組的設計，為本研究室同步之實驗數據，針對十一種手部動作，可達90%以上辨識率。軟體實驗中，應用相同之網路架構測試GBPN，平均辨識率可達80%以上。
以軟體印證GBPN網路可行後，對於硬體線路的設計，首重執行的效率與所需的晶片面積。利用具有管線和單一指令多資料流特性的一維心縮式陣列，做為電路設計的基本概念。電路上將分為三部分，包含前向網路單元、權植修正單元與記憶體。
目前，GBPN受限於晶片面積不足的因素，完成FFN-BLOCK、RAM模組，功能上僅能應用於案例模式。經由功能上及時序上軟體模擬與印證下，GBPN可正確運作。此外，GBPN應用在肌電圖分類中，經有效選擇輸入資訊，其網路結構可大幅減少，使所需運算時間縮短為原先之50%。

關鍵字

FPGA ； 心縮式陣列 ； 類神經網路 ； 肌電圖 ； 倒傳遞神經網路

並列摘要

Langue is the most important ability for human to communicate and express thoughts. Most of the time, hearing system or vocal organ obstacles cause the person to lose his ability to speak. These persons can make use of sign language, lip reading or paper and pen as tools to communicate with other person. However, person without special training cannot understand the sign language. Until now, there is still no effect auxiliary tool to assist hearing impaired person to communicate.
On the other hand, the electromyogram (EMG) is used extensively on diagnosing muscular or nerve pathological disorder. Additionally, EMG is also used in the control of prosthesis. Within these applications, the artificial neural network (ANN) is commonly used as the core of EMG identification.
In this study, a back-propagation neural network is realized on the FPGA chip that will be used in a multi-channel EMG system for hand gesture identification. First, a Matlab program is developed to test the general back-propagation neural network (GBPN). It is then realized on the FPGA chip. To put the emphasis on the throughput, the systolic architectures that have pipeline and parallel processing capability is used in the design of digital circuit. The digital circuit is divided into three parts, including feed-forward network unit (FFN-BLOCK), weight update unit (WUD-BLOCK) and memory (RAM). Due to the restriction of FPGA chip, only the FFN-BLOCK and memory parts are completed in this study.
The GBPN software is tested with an average identification rate over 80%. On the other hand, the function and timing simulation of the FPGA circuit demonstrate that the GBPN hardware can function correctly. Additionally, the characteristic and redundancy of GBPN input are examined. It is found that with proper selection of inputs, the GBPN can perform comparable with only one-third of input.

並列關鍵字

Systolic Array ； Back-Propagation Neural Network ； Artificial Neural Network ； FPGA ； Electromyogram

參考文獻

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