晶圓製造廠的設施規劃直接影響其生產效率與營運績效,良好的工廠佈置亦可縮短各晶圓之平均移動距離並降低在製品水準。對晶圓製造廠而言,因其複雜、再迴流的製程特性,以及特殊機台、安全法規、管線與人員維護等限制,導致其佈置困難度的增加。就目前而言,晶圓廠的佈置均以複製他廠為主。因速度在半導體製造業扮演著極重要的角色,晶圓廠的規劃者必須在短時間內完成整個工廠的佈置,因此一套有系統的設計規劃程序就顯得格外重要。 本文主要分為三大部分,第一部份為晶圓廠系統化設施規劃程序之模式建立。以Interbay為主,對整個晶圓廠的設計程序作一完整的探討與整合,利用快速且量化的計算模式,以系統化且更有效率的方式提供給決策者一較佳的設施佈置方案。透過此模式,當改變製程參數如產品比例與需求時,可以迅速計算所需之產能,得知各類型機台所需之機台數,作為產能規劃與評估之用。另外,也能藉由Interbay的搬運距離、IMHS所需之台車數以及晶圓的平均移動距離等績效指標,來協助評估各個佈置方案之優劣。 第二部分探討群組技術在晶圓廠的應用與限制。討論群組技術之效益,並於群組單元形成方面,導入ROC與HNPA_Revised兩種群組技術方法,在產品種類較為固定或製造流程相似度高時有其應用之價值,且在整體績效上群組技術確實有較佳之表現。 第三部分則為實際案例之探討。本文建立一套工業界認可之數據,以step-by-step的系統化程序作模式之建構。同時驗證本研究模式之正確性,並進一步利用案例來說明本研究流程之可行性。
Facility Design is crucial to the performance of wafer fabs in semiconductor industry. A proper facility design brings higher productivity, shorter average wafer moving distance and lower level of WIP. In regard to semiconductor manufacturing, the facility design is more difficult because of the complicated and long process flows, re-entrant characteristic, maintenance of machine, laws of industrial safety and constrains of pipe. Up to now, the new fab layout almost copy from other fabs. “Speed” plays an important role in semiconductor manufacturing. the available time for the design of wafer fab layout is short, and a fab designer needs to speed up the fab design procedure. So a practical and systematic fab design procedure becomes important. This research proposes a step-by-step approach to sequentially determine fab design parameters. The emphasis is the use of quick quantitative calculation and group technology to develop and evaluate initial fab design alternatives. By this modeling tools, we can help fab planner to change model parameters quickly (e.g., product mixes and demands) to answer “what-if” questions for actual or potential changes. Decision makers can then evaluate the performance of layout alternatives and select the best one. In regard to cell formation, we propose ROC and HNPA_Revised methods. In the condition of similar products or process routines, they can bring higher performance in some measurements, such as moving distance of Interbay, numbers of IMHS vehicle, average wafer moving distance, etc. Finally, we establish a set of data and examples in order to verify and validate this model.
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