低功率晶片在後擺置階段之電壓源區域建構及多重電壓源元件置換

Voltage Area Construction and Voltage Scaling at Post Placement Stage for Low Power IC Design

黃鉦凱(Cheng-Kai Huang)

指導教授 ： 陳美麗

中原大學/工學院/資訊工程研究所/碩士(2005年)

https://doi.org/10.6840/cycu200500314

摘要

隨著製程技術的進步，晶片上的元件數目大幅增加，如何節省功率消耗，是一個不可或缺的考量。本篇論文提出利用多重電壓源元件置換的方法，降低晶片的功率消耗。
相較於目前多重電壓源元件設計流程，我們提出一個在後擺置階段才進行電壓源區域建構及多重電壓源元件置換的演算法。在後擺置階段因為已經有元件擺置的位置，所以可以較精確的估算時序，而後進行多重電壓源元件置換。
本論文可以分成兩個主要步驟。首先利用標準元件的slack值，建出Critical Region Search Tree，然後找出適合使用高電壓源的區域。第二步驟為根據標準元件所在的電壓源區域，進行電壓源元件置換，並加入階層轉換器，若是在這個步驟做完後，有時序錯誤的情形發生，就利用置換不同驅動能力的標準元件，修復時序錯誤。
由實驗結果可以看到，在沒有時序錯誤發生的情形下，本論文提出的方法大約可以節省20%的功率消耗。

關鍵字

電壓源區域 ； 多重電壓源元件置換 ； 低功率設計 ； 後擺置階段

並列摘要

With the improvement in process technology, the number of cell on the ICs increases dramatically. Therefore it is essential to study the mechanism in saving the power consumption of an IC. In this paper, we propose a voltage scaling technique with multiple supply voltages to reduce the power consumption on a chip.
In contrast to the current multiple supply voltages design flow, we perform the voltage area construction and voltage scaling at post placement stage in stead of the synthesis stage. It is because after placement the timing may be estimated more accurately.
There are two major phases in our algorithm. In the first phase, the slack value of standard cells is utilized to construct a Critical Region Search Tree of smaller slack cells, and then the high voltage region is formed. In the second phase, according to the voltage region of standard cells, we perform voltage scaling and insert level converters. After this phase, if timing violation occurs, we apply gate sizing technique to fix timing violation.
Experimental results show that this proposed technique can reduce about 20% power consumption of a chip without any timing violation.

並列關鍵字

low power design ； voltage scaling ； post placement stage ； voltage area

參考文獻

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