Title

涵蓋實體訊號到網路系統行為層之無線網路QoS矽智財之驗證

Translated Titles

Wireless Networking QoS SIP Verification Covering Signal to Networking System Behavioral Levels

DOI

10.6828/KSU.2009.00053

Authors

鄭宇良

Key Words

嵌入式Linux驅動程式 ; 中介軟體 ; AMBA ; 階層式跨協定控制 ; 矽智財 ; Embedded Linux Driver ; Middleware ; AMBA ; HCLC ; SIP

PublicationName

崑山科技大學電子工程研究所學位論文

Volume or Term/Year and Month of Publication

2009年

Academic Degree Category

碩士

Advisor

陳朝烈

Content Language

繁體中文

Chinese Abstract

本論文提出支援無線網路跨協定之電子系統層級驗證(Electronic System Level; ESL),其中主要以服務品質(Quality of Service; QoS)矽智財與跨協定演算法為主要驗證標的,因此本文所謂電子系統層級,包含跨協定演算法軟體與QoS矽智財硬體電路,驗證目標是軟硬體共同設計(架構與演算法共同設計; Algorithm and Architecture Co-design; A/A Codesign)。我們設計嵌入式Linux之中介軟體(middleware)與驅動程式(Linux Driver),用以連結網路模擬器,整合上層跨協定控制軟體與矽智財FPGA硬體雛型,形成一個跨協定ESL驗證平台(Hierarchical Cross-Layer Control ESL; HCLC ESL),克服了傳統ESL驗證做不到的QoS、網路傳輸、實體硬體訊號與功耗之驗證。因此我們將ESL驗證向上延伸到跨協定演算法與網路通訊(networking),向下延伸到真實硬體效能之量測。在整個驗證流程中,我們使用NS-2網路模擬器提供無線網路情境以及通訊協定,因此HCLC ESL的使用者不必另外掛載(porting)通訊協定。而利用socket將網路的狀態(例如packet delay)傳達給HCLC控制器,這些控制器中包含實現在EDA工具中之軟體控制器以及以Linux Driver驅動之FPGA硬體控制器矽智財。對於FPGA而言,當中介軟體收到NS-2的資料後,透過驅動程式觸發SoC bus的協定,將網路狀態傳送到FPGA的矽智財中,矽智財接收到網路狀態進行計算之後重新發出控制訊號,控制訊號一樣由相同路徑返回到NS2,用以改變網路狀態,完成迴授控制的一次迴路。 本論文以IEEE 802.11e HCCA WLAN、IEEE 802.11e EDCA VANET、以及IEEE 802.16e Mobile WiMAX的跨協定QoS演算法與矽智財驗證作為實例,證明所提出的HCLC ESL驗證平台可適用在不同的無線網路技術。透過本論文所設計之中介軟體(middleware)與驅動程式(Linux Driver),能快速整合跨協定控制軟體與QoS矽智財,容易進行軟硬體共同驗證以及A/A共同設計,並且達到現有ESL驗證工具做不到的Networking與Control Algorithm的驗證,而使用真實硬體FPGA也達到實體訊號品質與功率消耗之驗證。

English Abstract

We propose an electronic system level (ESL) verification framework with Hierarchical Cross-Layer Control (HCLC) for wireless networking Quality of Service (QoS) Silicon Intellectual Property (SIP) verification covering physical signal to networking system behavioral levels. The primary objective of the proposed HCLC ESL verification is co-exploration of algorithm and architecture (A/A) pairs as well as software- hardware co-design. In the HCLC ESL verification platform, we design templates for middleware and Linux drivers in order to connect the network simulator, Electronic Design Automation (EDA) tools, and real Field Programmable Gate Array (FPGA). The platform extends verifications up to algorithmic and networking levels, and down to physical signal level. We use network simulator, NS-2, to provide networking scenarios and protocol stacks for wireless networking. The HCLC controllers receive network states via network socket constructed in the middleware. The HCLC controllers are distributed in software, EDA tools, and hardware SIPs in FPGA. On received data form NS-2/EDA, the middleware send network state to SIP in FPGA via Linux driver and System-on-Chip (SoC) bus protocol. After SIP finish calculating the next control according to the networking state, it uses the reverse way to return control signal to NS-2/EDA. Case studies including cross-layer QoS control algorithm for IEEE 802.11e HCCA Wireless Local Area Networks (WLAN), IEEE 802.11e EDCA Vehicular Ad hoc Networks (VANET), and IEEE 802.16e Mobile WiMAX show that the proposed HCLC ESL verification framework is generally applicable in different wireless technologies.

Topic Category 工程學院 > 電子工程研究所
工程學 > 電機工程
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Times Cited
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