透過您的圖書館登入
IP:3.235.246.51
  • 學位論文

整合SDRAM控制器、主僕式矽智財、與SoC匯流排分析儀之系統晶片設計架構

An SoC Design Framework Integrating SDRAM Controller, SIPs, and SoC Bus Analyzer

指導教授 : 陳朝烈
共同指導教授 : 王文壽(Wein-So Wang)

摘要


本論文主要探討高效率之矽智財設計與整合流程,並量測矽智財(Silicon Intellectual Property; SIP)實體訊號,以達到下列三個目標:1.使用統一塑模語言(Unified Modeling Language; UML)模型描述系統單晶片(System on chip; SoC)匯流排之行為,用以快速設計Master 與Slave wrappers;2. Master/Slave SIP之框架(framework),用以快速讓SoC設計者進行SoC整合;3. SoC Bus Analyzer,用以量測SIP真實硬體匯流排訊號並比對標準訊號進行相容性驗證,降低SIP設計以及SoC整合時之除錯困難度。 這三個目標分別由支援即時性設計之規格與描述語言 (Specification and Description Language – Real-Time; SDL-RT)、AMBA/FPGA Platform Development Kit (PDK)以及ModelSim來完成。SDL-RT實現快速設計Master & Slave wrappers的目標,PDK達成快速SoC整合的目標,ModelSim實現分析真實匯流排訊號的目標。 我們先以FPGA發展出SDRAM Controller SIP,並成功將SDRAM Controller快速的移植到PDK上,首先依據SDRAM Specification修改其Controller之參數(AC Electrical Characteristics),其次根據AMBA手冊的操作說明以及波形圖,繪製出訊息順序圖(Message Sequence Chart; MSC),並依照MSC產生SIP Wrapper的參數化有限狀態機(Finite State Machines; FSMs),以SIP Wrapper FSMs做為一個Master/Slave SIP之框架(framework),將SDRAM Controller快速包裝(Wrapping)成AMBA相容的SIP,並且運用AMBA SoC Bus Analyzer,在不影響原本bus protocol transactions的情況下,擷取匯流排訊號儲存至外部SDRAM中,交由ModelSim繪製出波形圖,快速找出包裝(Wrapping)SIP時的SoC Bus協定相容性的問題,有效地節省SIP開發時間。由這些wrapper FSMs以及分析儀,我們並開發兩種直接記憶體存取(Direct Memory Access; DMA)雛型,包含獨立DMA Master/Slave SIP以及可整合到其他SIP中的DMA控制器,藉由這些最基本的構成方塊組織成系統晶片設計架構,降低SoC整合時的複雜度。 以我們的開發方式,從暫存器傳輸級(Register Transfer Level; RTL)的研發到把SIP包成AMBA相容的SIP,都是在實體硬體板子上開發,省去在軟體上開發所花費的時間,有效地提高SIP與SoC整合的可信度並降低不確定性,因此我們所提出的框架為一快速設計、整合及驗證的平台。

關鍵字

SoC AMBA SIP Analyzer 嵌入式系統

並列摘要


The study focuses on efficient design and integration of Silicon Intellectual Properties (SIPs), as well as measurement of SIP physical signals to meet the following three objectives: 1. efficient design of master and slave wrappers by using the Unified Modeling Language (UML) model to describe System on Chip (SoC) bus behavior; 2. an SoC integration framework including master and slave SIP templates, memory controller, DMA and SoC bus analyzer to accelerate SoC integration; and 3. an SoC bus analyzer measuring physical hardware signals for bus protocol specification testing and thus to alleviate debugging from physical to system levels in the process of SoC integration. We exploit the Real-Time UML (RT-UML), SoC bus governed FPGA platform, and a waveform viewer reading test benches described in standard Hardware Description Language (HDL) such as Verilog. The RT-UML achieves fast design of master/slave wrappers, the FPGA platform reaches fast SoC integration with physical hardware prototype, and the waveform viewer accomplishes real world signal analysis. We begin at SDRAM controller and successfully transplant it to the FPGA platform. Firstly according to SDRAM specifications, we modify timing parameters according to the AC electrical characteristics. Secondly, according to the waveform defined in the AMBA specification, we draw out the Message Sequence Chart (MSC), and in accordance with the MSC we generate parameterized Finite State Machines (FSMs) for wrappers. Regarding the parameterized wrapper FSMs as templates, we wrap the SDRAM controller into an AMBA-compatible slave SIP. The AMBA SoC bus Analyzer, without interposing the bus transactions among SIPs under test, captures bus signals to external SDRAM. With programmable triggering conditions in complex logic, SoC engineers dump the signals before and after triggered point and analyze protocol compatibility using the waveform viewer. In this way, DMAs and user-defined ASICs are easily wrapped into platform-based and truly reusable SIPs. With the wrapper templates and the analyzer, we develop two types of direct memory access (DMA) prototypes including an independent DMA master/slave SIP and a dedicated DMA control framework that is integratible into memory-intensive SIPs. The wrapper templates, DMA prototypes, and the SoC bus analyzer constitute a reconfigurable SoC design framework. The statistical analysis suggests that the SoC design flow includes the proposed framework and gradually integrates verified SIPs. Therefore, providing real-world hardware rapid prototyping, the proposed framework effectively reduces complexity and uncertainty while increases reliability of SoC integration before the backend design stage.

並列關鍵字

SoC AMBA SIP Analyzer Embedded

參考文獻


[4] P. Magarshack, P. G. Paulin, “System-on-Chip beyond the Nanometer Wall,” Proceedings of Design Automation Conference (DAC), pp. 419-424, June. 2003.
[5] O. M. Group, “Unified modeling language,” http://www.uml.org/
[6] Martin, G. “UML for Embedded Systems Specification and design: Motivation and overview”. DATE 2002.
[7] L.B. Brisolara, M.F.S. Oliveira, R. Redin, L.C. Lamb, L. Carro and F. Wagner, “Using UML as Front-end for Heterogeneous Software Code Generation Strategies,” in Munich Design Automation and Test in Europe, pp. 504-509, March, 2008.
[8] C.F. Kao, I.J. Huang and C.H. Lin, “An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration,” in Proc. DAC, pages 477-482, 2007.

被引用紀錄


賴建豪(2010)。支援IEEE 802.16e/j/m與802.11e垂直漫遊之多標準QoS控制矽智財〔碩士論文,崑山科技大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0025-1908201010363200

延伸閱讀