以共濺鍍法開發鈦摻雜氧化銦鎵鋅通道層改善薄膜電晶體之電特性及可靠度

Improved Electrical Characteristic and Stability of Thin-Film Transistors with A Co-sputtered Ti-IGZO Channel

顏浩評

鈦摻雜 ； 氧化銦鎵鋅 ； 氧化矽鋯 ； 共濺鍍 ； 薄膜電晶體 ； Ti-doped ； α-IGZO ； ZrxSi1-xO2 ； Co-sputtering ； Thin film transistor

成功大學微電子工程研究所學位論文

2017年

碩士

王水進

繁體中文

本論文提出以共濺鍍技術改善薄膜電晶體之介電層與通道層，並進行其元件電特性量測、分析與可靠度之研究。 本研究主要分為兩部分，第一部分為延續本實驗室先前研究之氧化矽鋯介電層於氧化銦鎵鋅薄膜之應用，進一步探究其之可靠度特性，並設計二氧化鋯與二氧化矽介電層之堆疊結構，以分析不同材料界面於元件可靠度之影響；第二部分以共濺鍍製程技術結合氧化銦鎵鋅與二氧化鈦製備鈦摻雜氧化銦鎵鋅薄膜(Ti-doped IGZO)，藉由調變濺鍍功率之比例，調整材料組成與特性，並進一步分析其應用於薄膜電晶體之電特性與可靠度。此外，為進一步提升元件特性，本論文亦討論鈦摻雜氧化銦鎵鋅通道層經沉積後退火製程(post deposition annealing, PDA)對材料特性、電特性與可靠度等之影響。 於本論文第一部分，首先探討觀察二氧化鋯與二氧化矽之介電層堆疊結構應用於氧化銦鎵鋅薄膜電晶體時，不同的界面於電性與可靠度之影響。由實驗結果得知，二氧化矽與氧化銦鎵鋅有較優異的界面品質與較少的界面缺陷，證實藉由適當含量之Si元素的摻入，有助於減少通道層/介電層之界面缺陷密度。本研究進一步針對此元件進行可靠度之分析，其最大臨界電壓的偏移分別從原先的1.165 V與-0.898 V改善至0.776與-0.491 V，元件可靠度獲得大幅的改善。 於本論文第二部分，為改善氧化銦鎵鋅薄膜之高缺陷密度，藉由摻入易氧化之鈦元素抑制氧空缺的產生，以提升氧化銦鎵鋅通道層之薄膜品質。實驗結果顯示，因鈦元素具易氧化之材料特性，進而捕捉氧氣以填補薄膜的氧空缺，透過共濺鍍方式摻入於氧化銦鎵鋅薄膜，可使氧化銦鎵鋅薄膜之能隙增加與施體能階減少，可進一步抑制漏電流。此外，經由鈦元素之摻雜，可使氧化銦鎵鋅薄膜之缺陷密度降低，改善元件可靠度。而具鈦摻雜之氧化銦鎵鋅薄膜，不易因退火製程而造成氧原子脫離而形成氧空缺，因此可承受較高溫環境下的退火修補與活化，進一步改善其電特性與可靠度。 本論文所開發之鈦摻雜氧化銦鎵鋅薄膜電晶體，由實驗結果顯示，摻入適量鈦元素之氧化銦鎵鋅，除了改善薄膜的品質更有助於減少介電層/通道層界面之缺陷密度，其中以具鈦摻雜比例為1.0 %之鈦摻雜氧化銦鎵鋅通道層的薄膜電晶體，經400°C氮氣環境下的退火，可獲得最佳電晶體特性與可靠度：於電特性部份，其元件電流開關比為1.65×10^8、次臨界擺幅為90 mV/dec、載子遷移率為24.2 cm^2/V∙s、界面缺陷密度為1.09×10^12 cm^-2eV^-1；於可靠度部分，正負偏壓應力之臨界電壓偏移分別為0.157 V和-0.093 V。此實驗結果已達成本論文於改善氧化銦鎵鋅薄膜電晶體之元件電特性與可靠度之標的。 本論文成功以共濺鍍製備鈦摻雜氧化銦鎵鋅通道層並應用及改善薄膜電晶體之界面品質、閘極控制能力與元件可靠度，及有助於未來顯示技術之電子產品特性提升與應用。

The use of a co-sputtered Titanium doped indium gallium zinc oxide (Ti-IGZO) channel with zirconium silicon oxide (Zr0.85Si0.15O2) as gate dielectrics to improve reliability of thin-film transistors (TFTs) is presented. Experimentla studies reveal that oxygen vacancies in post deposition annealed (PDA) Ti-IGZO Channel is decreased after Ti incorporation and stability of the TFTs could be considerably improved. It is attributed to Ti is with a stong oxidibility which leads to bandgap enlargement, donor energy level lowering, and trap state density suppression for the Ti-IGZO channel. Experimental results reveal that Ti-IGZO channel prepared at a power ratio of IGZO:TiO2=80 W:25 W with a PDA at 400°C and with a 9±1-nm-EOT Zr0.85Si0.15O2 layer shows the best device performance with the on/off current ratio, the subthreshold swing, the threshold voltage shift after 1000 sec positive/negative gate-bias stress are of 1.65×10^8, 0.09 V/dec, and 0.157 V/-0.093 V, respectively.

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