漸進接面對於高壓金氧半電晶體性能與可靠度之影響

Effect of Gradual Junction on Performance and Reliability of High Voltage MOS Transistors

10.6844/NCKU.2015.01542

艾登仁

高壓金氧半場效電晶體 ； 漸進接面 ； 熱載子導致之退化 ； 電腦輔助設計模擬 ； HVMOSFET ； gradual junction ； off-state breakdown ； hot-carrier-induced degradation ； TCAD simulation

成功大學微電子工程研究所學位論文

2015年

碩士

陳志方

英文

在本論文中，探討了兩種相對應製程，傳統接面與漸進接面的高壓(HV)金氧半場效電晶體(MOSFET)元件之特性，包含了其崩潰電壓的差異以及崩潰機制，與受熱載子影響產生的退化及其元件生命週期之完整性議題。 首先，對於高壓金氧半場效電晶體元件在市場中的應用與其優點特色作闡述。接著描述研究之動機，對於使用漸進接面之高壓金氧半電晶體在其與傳統接面比較下，崩潰電壓增進之現象，其延伸之研究。本論文中亦會介紹元件崩潰之機制、熱載子效應與元件可靠度之關係、以及分析元件特性之電腦輔助設計(TCAD)模擬軟體。 基礎簡介後，呈現本研究中使用傳統接面以及漸進接面之製程差異，並且陳述元件的結構和量測的設定與方法，其中包括：元件電流ID-VD 、線性區電流ID-VG、基板電流Isub-VG以及崩潰電壓VBD之量測。 本研究的內容，主要觀察到使用漸進接面之高壓金氧半場效電晶體之元件，在崩潰電壓的方面，相較與使用傳統接面的高壓金氧半場效電晶體，有較高的耐壓特性；而這個現象在更大的元件尺寸中更為明顯。因此使用電腦輔助設計(TCAD)模擬軟體來分析元件在不同條件下的電場，以及其衝擊離子化效應(Impact Ionization)之分佈，進一步研究其崩潰的機制以及為何使用漸進接面的大尺寸元件可以獲得更加的耐壓效果。 而本研究之另一個重點為探討漸進接面之元件在熱載子可靠度方面，與傳統接面之高壓金氧半電晶體之差異。文中先敘述了熱載子可靠度量測實驗的設置，並且佐以電腦輔助設計模擬之結果，分析兩者在熱載子可靠度以及元件生命週期上並沒有太大的差異，最後元件的生命週期對基板電壓做出元件生命週期斜率圖，對於未來以漸進接面製程製造之高壓金氧半場效電晶體元件的研究可以有更多的參考。

In the thesis, special process manufactured high voltage metal-oxide-semiconductor field effect transistors (HV-MOSFET) with gradual junction was studied. Devices’ breakdown voltage, hot-carrier-induced degradation and lifetime were compared with high-voltage devices with traditional junction. The different mechanism and device lifetime between the devices was investigated. First, the advantages and the usage of HVMOSFET were illustrated. The motivation of further studying high-voltage device with gradual junction was presented. Due to the fact that high voltage devices with gradual junction had better off-state breakdown voltage performance comparing with device with traditional junction. Thus, the mechanism of devices’ off-state breakdown, relationship between hot carrier effect and device reliability and lifetime were performed in the thesis. Also, technology computer aid design (TCAD) was utilized to discuss the details of the devices. Therefore, the differential between high-voltage devices with traditional junction and gradual junction were presented in the second part of the thesis, and the structure of the devices and the measurement methodology and setup were also described. Including device current ID-VD, linear region current ID-VG, substrate current Isub-VG and off-state breakdown voltage VBD. The main part of the thesis were focus in part three and part four. In part three, the observation of improvement of off-state breakdown voltage in devices with gradual junction was proved. And also indicated that the improvement of off-state breakdown voltage was even better in bigger dimension devices with gradual junction. As a result, TCAD was used to analysis the mechanism between these two kinds of devices, for instance, the electric field contour, impact ionization rate contour. The reliability issue was discussed in part four, which the hot carrier stress was applied to study the degradation of the devices. The measurement setup and stress condition were presented. TCAD simulation software was used to confirm the measurement data. At the end, the plot of devices’ lifetime versus substrate current was demonstrated. It can be used to predict the lifetime of high-voltage devices’ lifetime if the structure is demanded in application.

1. [1] Li, Y. Q., C. A. T. Salama, M. Seufert, P. Schvan, and Mike King (1997), “Design and Characterization of Submicron BiCMOS Compatible High-Voltage NMOS and PMOS Devices,” IEEE Transactions on Electron Devices, 44(2), pp. 331~338
   連結：
2. [2] B. S. Doyle, Member, IEEE, and K. R. Mistry, Member, IEEE "Anomalous Hot-Carrier Behavior for LDD p-Channel Transistors " IEEE Electron Device Letters VOL.14 No.11 November, 1993
   連結：
3. [4] Zitouni, M., F. Morancho, H. Tranduc, P. Rossel, J. Buxo, I. PageÁs, and S. Merchant (1999), “A new lateral power MOSFET for smart power ICs: the ``LUDMOS concept'”, Microelectronics Journal , 30(6), pp. 551~561
   連結：
4. [6] Mikoshiba, H., T Horiuchi, and K. Hamano (1986), “Comparison of Drai Structures in n-Channel MOSFET’s,” IEEE Transactions on Electron Devices, vol.ED-33, no. 1, 1986, pp.140~144
   連結：
5. [7] Ogura, S., P. J. Tsang, W.W. Walker, D.L. Critchlow, and J.F. Shepard (1981), “Elimination of hot electron gate current by the lightly doped drain-source structure,” IEEE Electron Devices Meeting, International, 27, pp. 651~654
   連結：
6. [9] Jone F. Chen, Member, IEEE, Kuen-Shiuan Tian, Shiang-Yu Chen, Kuo-Ming Wu, J. R. Shih, and Kenneth Wu "Mechanisms of Hot-Carrier-Induced Threshold-Voltage Shift in High-Voltage p-Type LDMOS Transistors" IEEE Transactions on Electron Devices, VOL. 56, NO. 12, DECEMBER 2009
   連結：
7. [10] Jone F. CHEN, Kuo-Ming WU, J. R. LEE, Yan-Kuin SU, H. C. WANG, Y. C. LIN , and S. L. HSU "Characteristics and Improvement in Hot-Carrier Reliability of Sub-Micrometer High-Voltage Double Diffused Drain Metal–Oxide–Semiconductor Field-Effect Transistors" Japanese Journal of Applied Physics Vol. 46, No. 4B, 2007, pp. 2019–2022
   連結：
8. [11] Jone F. Chen, Tzu-Hsiang Chen and Deng-Ren Ai “Two-stage hot-carrier-induced degradation of p-type LDMOS transistors” IEEE Electronics Letters 6th November 2014 Vol. 50 No. 23 pp. 1751–1753
   連結：
9. [12] Chin-Rung Yan, Jone F. Chen, Chung-Yi Lin, "Characteristics of Lateral Diffused Metal–Oxide–Semiconductor Transistors with Lightly Doped Drain Implantation through Gradual Screen Oxide" Japanese Journal of Applied Physics 52 (2013) 04CC07
   連結：
10. [13] Zanella, A. ; Dept. of Inf. Eng., Univ. of Padova, Padua, Italy "Internet of Things for Smart Cities" ,Internet of Things Journal, IEEE, Vol.1, Issue 1 P.22 - P.32
    連結：
11. [14] Hodges, S. ; Microsoft Res. Cambridge, Cambridge, UK, "Prototyping Connected Devices for the Internet of Things" Computer ,Volume:46 , Issue: 2, P.26-P.34
    連結：
12. [17] Apple - products
    連結：
13. [20] ARM - Internet of things
    連結：
14. [22] Samsung video wall
    連結：
15. [24] Jone F. Chen, Member, IEEE, Chin-Rung Yan, Yin-Chia Lin, Jhen-Jhih Fan, Sheng-Fu Yang, and Wen-Chieh Shih, "Analysis of GIDL-Induced OFF-State Breakdown in High-Voltage Depletion-Mode nMOSFETs" IEEE Transactions on Electron Devices, VOL. 58, NO. 6, JUNE 2011
    連結：
16. [25] Oleg Semenov, Andrzej Pradzynski, Member, IEEE, and Manoj Sachdev, Senior Member, IEEE,"Impact of Gate Induced Drain Leakage on Overall Leakage of Submicrometer CMOS VLSI Circuits" IEEE Transactions on Semiconductor Manufacturing, VOL. 15, NO. 1, FEBRUARY 2002
    連結：
17. [27] Parke, S.A. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Moon, J.E. ; Wann, H.-J.C. ; Ko, P.K. "Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model" IEEE Electron Devices Transactions on (Volume:39 , Issue: 7 ) p.1694 - p.1703
    連結：
18. [28] Yang-Kyu CHOI, Daewon HA, Tsu-Jae KING and Jeffrey BOKOR" Investigation of Gate-Induced Drain Leakage (GIDL) Current in Thin Body Devices: Single-Gate Ultra-Thin Body,Symmetrical Double-Gate,and Asymmetrical Double-Gate MOSFETs" Japan Journal Apply Physics Vol. 42 (2003) pp. 2073–2076
    連結：
19. [29] Ja-Hao Chen, Shyh-Chyi Wong, and Yeong-Her Wang, Member, IEEE "An Analytic Three-Terminal Band-to-Band Tunneling Model on GIDL in MOSFET" IEEE Transactions on Electron Devices, VOL. 48, NO. 7, JULY 2001
    連結：
20. [30] Ja-Hao Chen, Shyh-Chyi Wong, Member, IEEE, and Yeong-Her Wang, Member, IEEE "DC Pulse Hot-Carrier-Stress Effects on Gate-Induced Drain Leakage Current in n-Channel MOSFETs" IEEE Transactions on Electron Devices, VOL. 48, NO. 12, DECEMBER 2001
    連結：
21. [33] Hu, C. M., C. T. Simon, H. Fu-Chieh, P. K. ko, T. Y. Chan, and K. W. Terrill (1985), “Hot-Electron-Induced MOSFET Degradation-Model, Monitor, and Improvement”, IEEE Journal of Solid-State Circuits, 20, pp. 295~305
    連結：
22. [35] Silvaco "Guide to using TCAD with examples" 4701 Patrick Henry Drive, Bldg. 2 Santa Clara, CA 95054,2009
    連結：
23. [39] Agilent Technologies, B1500A semiconductor device analysis introduction
    連結：
24. [41] Everett E. King, Ronald C. Lacoe and Janet Wang-Ratkovic "The Role of the Spacer Oxide in Determining Worst-case Hot-Carrier Stress Conditions for NMOS LDD Devices "IEEE 00CH37059 38"Annual International Reliability Physics Symposium, San Jose, California, 2000
    連結：
25. [3] Shi, Y., N. Feilchenfeld, R. Phelps, M. Levy, M. Knaipp, and R. Minixhofer (2011), “Drift Design Impact on Quasi-Saturation & HCI for Scalable N-LDMOS”, IEEE International Symposium on Power Semiconductor Devices & IC's, San Diego, May, pp.215~218
26. [5] Klein, N., S. Levin, G. Fleishon, S. Levy, A. Eyal, and S. Shapira (2008), “Device design tradeoffs for 55v LDMOS driver embedded in 0.18 micronplatform”, IEEE 25th Convention of Electrical and Electronics Engineers in Israel, 2008. IEEEI 2008., Eilat, December, pp. 736~740
27. [8] Jone F. Chen, Member, IEEE, Kuen-Shiuan Tian, Shiang-Yu Chen, Kuo-Ming Wu, J. R. Shih, and Kenneth Wu "An Investigation on Anomalous Hot-Carrier-Induced On-Resistance Reduction in n-Type LDMOS Transistors" IEEE Transactions on Device and Materials Reliability, VOL. 9, NO. 3, SEPTEMBER 2009
28. [15] POREX Filtration division - flouride reduction
29. http://www.porexfiltration.com/applications/tubular-membrane-app/fluoride-reduction/
30. [16] JR East Company – North Land Shinkansen
31. http://www.jreast.co.jp/tc/routemaps/hokurikushinkansen.html
32. https://www.apple.com
33. [18] BMW – i8
34. http://www.bmw.com.tw/com/tw/newvehicles/i/i8/2014/showroom/
35. [19] Home electronics products
36. https://www.pinterest.com/topproductshop/home-electronic-products/
37. http://www.arm.com/zh/markets/internet-of-things-iot.php
38. [21] AWWA – sky whale
39. https://www.behance.net/gallery/AWWA-Sky-Whale-Concept-Plane/11891085
40. http://www.samsung.com/us/system/b2b/resource/2014/01/02/Videowall-Display-Solutions.pdf
41. [23] High Voltage MOSFET Technology, Models, and Applications Vaidyanathan Subramanian, PhD 200mm Foundry Enablement. IBM Systems and Technology Group (STG)
42. [26] Chen, J. ; University of California, Berkeley, CA ; Chan, T.Y. ; Chen, I.C. ; Ko, P.K. "Subbreakdown drain leakage current in MOSFET" Electron Device Letters, IEEE (Volume:8 , Issue: 11 ) p.515 - p.517
43. [31] C. C. Hu, Pearson "Modern Semiconductor Devices for Integrated Circuits" 2010 Page 103
44. [32] Bae, K., M. Jin, H. Lim, L. Hwang, D. Shin, J. Park, J. Heo, J. Lee, J. Do, I. Bae, C. Jeon, and J. Park (2011), “Behaviors and physical degradation of HfSiON MOSFET linked to strained CESL performance booster”, Reliability Physics Symposium (IRPS), 2011 IEEE International, Monterey, April, pp. PL.1.1~PL.1.5
45. [34] Sim Poh Ching ; X-FAB Sarawak Sdn. Bhd., Kuching, Malaysia ; Yook Hyung Sun ; Chu Tsui Ping "Optimization of hot carrier resistance for 0.18µm CMOS technology" Electronic Manufacturing Technology Symposium (IEMT), 2008 33rd IEEE/CPMT International
46. [36] "Athena User’s Manual" Silvaco, Inc. 4701 Patrick Henry Drive, Bldg. 2 October 30, 2013 Santa Clara, CA 95054
47. [37] "Atlas User Manual - DEVICE SIMULATION SOFTWARE" Silvaco, Inc. 4701 Patrick Henry Drive, Bldg. 2 November 27, 2013, Santa Clara, CA 95054
48. [38] Silvaco “TCAD World Leader” Silvaco engineered excellence.
49. https://www.testworld.com/used-electronic-test-equipment/keysight-agilent-parametric-test-systems/keysight-agilent-b1500a-semiconductor-device-parameter-analyzer-characterization-system-mainframe-easyexpert/
50. [40] Swin Super Solution & Service
51. http://www.3-.com.tw/fengxi/front/bin/ptdetail.phtml?Part=darkbox&Category=40
52. [42] M.M. Lunenborg, H.C. de Graaff, A.J. Mouthaan, J.F. Verweij "Anomalous NMOSFET Substrate Current Behavior at Accelerated Hot-Carrier Stress Conditions" Solid State Device Research Conference, 1995. ESSDERC '95. Proceedings of the 25th European
53. [43] J. R. Hook, H. E. Hall "Solid State Physics, 2nd Edition" John Wiley & Sons, Chichester (1991)
54. [44] Bart V Van Zeghbroeck, "Principles of Semiconductor Devices and Heterojunctions Paperback", University of Colorado (2007)