近年來隨著可攜式的電子產品急速地增加,電子產品趨於更輕薄、短小的取向,將電路積體化與減少外部元件是必然的趨勢,以及低功耗也是電子產品考量的因素之一。 在傳統的低壓差線性穩壓器中,如果要推動較大尺寸的功率電晶體時,會花比較久的反應時間,主要的原因是功率電晶體的閘端會有很大的寄生電容,為了改善推動功率電晶體的反應時間,本論文在傳統的低壓差線性穩壓器加入電壓緩衝器,利用電壓緩衝器高輸入阻抗以及低輸出阻抗的特性,對功率電晶體閘端的寄生電容進行快速的充放電,以改善反應時間。 本論文電路所使用的製程為TSMC 0.35μm 2P4M Mixed Signal CMOS 5V。設計的規格在輸入電壓2V~5V間,能提供1.8V的輸出電壓。加入電壓緩衝器後模擬結果顯示,在輸出電壓1.8V與負載電流100mA時,最大Dropout Voltage為230mV,在重載電流100mA下降至輕載電流5mA,最大穩定的時間為1.5μs改善至0.77μs,線性調節率從原本0.97mV/V改善至0.46mV/V,負載調節率改善了50%,電源拒斥比在10kHz為-39.2dB,總消耗靜態電流為31.8019μA。
In conventional low-dropout linear regulator, it takes more time to push the huge size power transistor because the great parasitic capacitance in the gate of the power transistor. In order to improve the response time to push power transistor. A voltage buffer is added in conventional low-dropout linear regulator in this paper. The voltage buffer, which has the characteristic of a high input impedance and low output impedance, Then, the parasitic capacitance in the gate of the power transistor will charge and discharge quickly by the current to improve the response time. The proposed circuit is designed by using TSMC 0.35μm 2P4M Mixed Signal CMOS 5V technology. The design specification is shown that the output voltage is 1.8 V when the input range is from 2 V to 5 V. The Simulation results show that when voltage buffer circuit was added, the maximum dropout voltage is 230mV when the output voltage is 1.8V and output current is 100 mA. the heavy load current 100mA down to light load current 5mA, the maximum response time improved to 1.5μs from 0.77μs, line regulation improved to 0.97mV / V from 0.46mV / V, load regulation improved to 50%, power supply rejection is -39.2dB at 10kHz, total quiescent current consumption 31.8019μA.
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