1.2伏特十位元連續逼近式類比數位轉換器設計與製作

The Design and Implementation of 1.2V 10-bits Successive Approximation Register Analog-to-Digital Converter

陳得勤(De-Chin Chen)

指導教授 ： 呂啟彰

國立虎尾科技大學/電機資訊學院/電機工程研究所/碩士(2015年)

摘要

在混合訊號的設計電路中，需要將類比訊號轉成數位訊號來進行處理，因此類比數位轉換器成為一個很重要的介面電路。而在各種類比數位轉換器電路中，連續逼近式數位類比轉換器具有低功耗及良好的轉換精確度，所以本論文以連續逼近式架構進行設計，其整體電路包含取樣與保持電路、比較器、數位類比轉換電路、時脈產生器和逐漸逼近暫存器；使用拔靴帶式開關以改善取樣保持電路的導通電阻及線性度問題；在數位類比轉換電路上，則使用傳統單端電容式架構、傳統差動電容式架構、結合雙取樣與傳統電容式架構和結合雙取樣與C-2C電容式架構等四種架構，並比較四種架構的優缺點在降低整體電容值、降低面積及功率消耗找到平衡點。
本論文中，使用TSMC 0.18μm 1P6M的製程，來實現結合雙取樣與C-2C電容式十位元數位類比轉換器。其電源電壓為1.2伏特，取樣頻率為727kHz，當輸入訊號為13.5KHz時，經由佈局後模擬可得到SFDR與SNDR分別為57.5dB 與56.3dB、有效位元數為9.06位元、差值非線性介於-0.7~0.95 LSB之間、積分非線性介於-1.22~1.48 LSB之間、功率消耗約為21.9μW，佈局後核心晶片面積為0.21×0.26mm2，此電路架構模擬結果與傳統差動電容式架構結果相比較，此架構可降低整體82%晶片面積以及降低74%功率消耗。

關鍵字

連續逼近式 ； 類比數位轉換器

並列摘要

In mixed-signal circuit, converting analog signals to digital signal is needed for processing, so analog-to-digital converter has become an important interface circuits. Among various analog-to-digital converters, successive approximation register digital-to-analog converter consumes low power and had high resolution feature. As a result, successive approximation register architecture is adopted in this thesis. The SAR ADC includes sample-and-hold circuit, a comparator, digital to analog convertor, clock generator and successive approximation register; using bootstrap switches to improve on-resistance and linearity for sample-and-hold circuit. In the digital-to-analog convertor, we use four kind of ADC, conventional single-ended capacitive architecture, conventional differential capacitive architecture, combined dual sampling with conventional capacitive architecture and combined dual sampling with C-2C capacitive architecture, and compare the four kind of architecture, find the balance between the overall capacitance value, layout area and power consumption.
In this paper, implement a 10-bits combination dual sampling with C-2C capacitive digital-to-analog converter in TSMC 0.18μm CMOS 1P6M process. The power supply voltage is 1.2V, the sampling frequency is 727kHz, when the input signal frequency is 13.5KHz, the post-simulation of the SFDR and SNDR are 57.5dB and 56.3dB, the resolution is 9.06 bits, he peak DNL is -0.7 ~ 0.95 LSB, the peak INL is -1.22LSB ~ 1.49LSB, and the power dissipation is about 21.9μW, the layout area is 0.217 × 0.268mm2, The circuit architecture simulation results are compared with the traditional differential capacitive, this architecture reduces 82% chip area and 74% power consumption.

並列關鍵字

Successive Approximation ； Analog-to-Digital Converter

參考文獻

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