Title

適用於助聽器之低功率噪音消除設計

Translated Titles

Low Power Noise Reduction Design for Hearing Aids Application

DOI

10.6842/NCTU.2009.01030

Authors

蔡政君

Key Words

噪音消除 ; 頻譜刪減 ; 助聽器 ; 熵值 ; 語音偵測 ; noise reduction ; spectral subtracion ; voice activity detection ; entropy ; hearing aids ; hardware implementation ; filter bank

PublicationName

交通大學電子工程系所學位論文

Volume or Term/Year and Month of Publication

2009年

Academic Degree Category

碩士

Advisor

張添烜

Content Language

繁體中文

Chinese Abstract

噪音消除是助聽器中的關鍵問題。為了補償患者的聽力損失,助聽器需要對輸入聲音加以放大,如此一來必需要以噪音消除設計來增進在噪音環境下的聲音品質和辨識度。在整合的助聽器系統中,為了延長電池使用壽命及最小化系統的體積,我們需要低功率的設計。 在此論文中,我們提出一套適用於助聽器的低功率噪音消除設計,其中包含了以熵值為基礎的語音偵測,及以濾波器組為基礎的頻域刪減。以熵值為基礎的語音偵測可在噪音環境下區分該時段是語音訊號或是沉默區間。以filter bank為基礎的頻域刪減估計噪音量值,並根據以熵值為基礎的語音偵測之結果做不同的頻域刪減。關閉機制在噪音量值低於一固定閥值時,停止頻域刪減之作動以節省耗電。透過降低運算複雜度,此演算法針對低功率的硬體設計作了最佳化設計。從實驗結果可以得知,平均區段噪訊比增進了6.27dB。PESQ分數則平均增進了0.316分。 最後此演算法在聯華電子90奈米CMOS製程下完成硬體實現。工作頻率為6百萬赫茲。為了節省面積及耗電,我們採用折疊硬體設計。基於資料存儲之需要,我們使用了1.536千位元組的靜態隨機存取記憶體。若包含靜態隨機存取記憶體,估計需要的邏輯閘約為101,697個。如不包含靜態隨機存取記憶體,則估計需要的邏輯閘約為80,628個。耗電量則為2.927×10^(-4)瓦。

English Abstract

For hearing aids application, the amplification of input sound is needed in order to compensate the hearing loss of the patient. Thus noise reduction is required to improve speech quality and intelligibility under noisy environments. For integrated hearing aids system, low-power design is necessary such that the battery life can be expended and the system volume can be minimized. In this thesis, we propose a low power noise reduction design for hearing aids application with entropy-based voice activity detection and filter bank-based spectral subtraction. The entropy-based voice activity detection distinguishes the speech period from the silence period in noisy environment and makes the decision whether it is voice active or not. The filter bank-based spectral subtraction estimates noise level and performs different spectral subtraction schemes based on the result carried out by the entropy-based voice activity detection. Off mechanism turns off the spectral subtraction process if noise level lies below a fixed threshold in order to reduce power consumption. The proposed algorithm is optimized for low power hardware design by minimizing the calculation complexity. From simulation results, the average segment SNR improvement is 6.27dB and the average PESQ score is elevated by 0.316. The final design is implemented by UMC 90nm CMOS technology with high VT cell library. The clock frequency is 6MHz. For the hardware architecture, folding technique is adopted to save area and to reduce power consumption. For data storage, 1.536K Bytes of SRAM is utilized. The total estimated gate count is 101,697 including SRAM and 80,628 excluding SRAM. The total power consumption is 292.7μW.

Topic Category 電機學院 > 電子工程系所
工程學 > 電機工程
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