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  • 學位論文

泛用於無線區域網路之高增益低雜訊且低功耗混頻器及三頻帶圓極化天線設計

A High Gain Low Noise Mixer with Low Power Consumption for WLAN Application and A Triple Band Circularly Polarized Antenna

指導教授 : 周復芳

摘要


本論文討論主要分為三部分,其中所提出電路之晶片製作皆由TSMC 0.18 μm mixed-signal/RF CMOS 1P6M製程來實現; 而天線部分採用厚度1.6mm的FR4板材完成。   第一部分為低雜訊混頻器的設計,利用串接低雜訊放大器的架構於轉導級,且於輸入端使用跨接電容於電晶體閘極到源級之間,第一級輸入訊號所接到的差動對以一電晶體組合在一起,形成共同電流源,此做為控制電流源的電晶體同時可達到協助輸入匹配的效果。除了轉導級所造成的雜訊抵銷條件外,串接架構本身所造成的高增益串接在系統中亦造成低雜訊特性,同時利用轉導級跨接電感技術,使寄生電容所造成的頻率響應被抵消,整體3dB頻寬將可不被壓縮;使我們得到以下優良的FOM值及其他量測結果。根據量測結果顯示:本混頻器匹配的S參數在操作頻率5~6GHz皆在-10dB以下,同時具有高功率增益值26.7~27dB,雜訊指數為7.3~8dB,於最高增益情況下IIP3為-12dBm,且整體功率損耗為11.32mW,FOM值為15.5dB。   第二部份之電路設計預期在保持高增益低雜訊的情況下達成低功耗混頻器,以此考量下,以不增加DC路徑上的電流,輸入級使用CG組態且增加額外訊號路徑以得到較高的等效轉倒值,將雜訊源到輸入端的寄生電容路徑以負回授組態降低;為彌補負回授路徑所造成的低輸入阻抗值,使用正回授路徑增加輸入阻抗值,且增加整體增益值,切換開關級則以PMOS取代傳統使用NMOS的架構,可降低電壓頭部空間,且使切換開關所造成的雜訊值不經由寄生電容所形成的小訊號路徑回流至轉導級。藉上述之改良技術,可得到以下量測結果:S參數在操作頻率5~6GHz階在-10dB下,同時具有高功率增益值25dB,雜訊指數為3.9~4.2dB,於最高增益情況下IIP3為-8dBm,且整體功率損耗降為3.92mW,可得FOM值提升至23.67dB。   第三部分提出新型三頻圓極化印刷天線架構設計,此天線主要由兩個圓板、兩條不等長的弧型輻射路徑及一個L形狹長微帶線訊號饋入端。該天線可以提供2.5GHz頻段的S參數33%阻抗帶寬比,在3.5GHz為25%,5.2GHz則為9.79%。軸向比帶寬在2.5GHz、3.5GHz及5.2GHz則分別為6.2%、11.8%及11.4%。該天線製作在FR4基板上。操作頻率覆蓋在2.5GHz、3.5GHz和5.2GHz的頻帶上,使得天線可以用在WiMax和WLAN應用。

並列摘要


This paper consists of three parts. All the proposed circuits were implemented in TSMC 0.18μm mixed-signal/RF CMOS 1P6M technology; and the antenna design is fabricated on an FR4 substrate.  Part I, It’s a design of low noise mixer, the trans-conductance stage is implemented with low-noise amplifier cascade structure, a cross capacitance was connected between the terminal gate and source of the input stage transistor, and the input differential pair was combined together by a current source transistor, the function of this transistor is not only as a current controller but also effects the input impedance to achieve a suitable value. The trans-conductance cause the noise cancelling, in addition to this, the first stage consist of cascade architecture and it provide a high power gain to reduce the noise factor in the overall system; for switching pairs, the parasitic capacitance resulting frequency response is cancelled by an additional inductive peaking, the conversion gain versus operation frequencies will become flat; in other words, overall 3dB bandwidth will not be compressed; the following techniques gives us an excellent FOM values. According to the measurement results showed that: The S parameter are blow to -10 dB for operation frequency band 5~6GHz, and it has high conversion gain from 26.7dB to 27dB, a flat DSB noise figure 7.3~8dB, at the frequency 5.2GHz with the maximum conversion gain, the IIP3 is -12dBm, and the power consumption is 11.32mW. The FOM is 15.5 dB.   Part II, the mixer design is expected to maintain a high gain and low noise. In addition, low power consumption is an important aim, with the consideration, in order create a high conversion gain but not to increase the current on the DC path, using the CG configuration as the input stage and an additional signal path is used to increase the equivalent value of trans-conductance, it implement by a negative feedback path to turn down the noise comes from gate leakage through the input parasitic capacitance path to source; to make up the low input impedance value caused by the negative feedback path, use positive feedback path to increase the input impedance value and increase the overall gain value, switch-pairs implement with PMOS transistors, instead of the traditional NMOS architecture; in this way, it can reduce the voltage headroom, and the noise source caused by the switching pairs will not leakage from parasitic to affect the trans-conductance stage. As above-mentioned improve techniques, measurement results can be obtained as the following: S parameter in the operating frequency 5 ~ 6GHz bands is below to -10dB, and it has high power gain 25dB, noise figure of 3.9 ~ 4.2dB, in the case of the highest gain IIP3 is measured as-8dBm, and the overall power consumption is reduced to 3.92mW, available FOM value increased to 23.67dB. Part III, In this proposed antenna architecture, the triple-band printed monopole antenna with triple band circular polarization is presented. The antenna generates circular polarization by two circular patches and a L shape strip. The proposed antenna can provide impedance bandwidths of 33% for 2.5GHz band, 25% for 3.5GHz band, and the 9.79% for 5.2GHz band, respectively. The axial-ratio bandwidths achieved 11.4% for 2.5GHz, 6.2% for 3.5GHz, and the 11.8% for 5.2GHz, respectively. The proposed antenna is fabricated on FR4 substrate. The operating triple frequencies cover 2.5GHz, 3.5GHz and 5.2GHz, so that the antenna could be used in WiMax and WLAN application.

參考文獻


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