微晶矽薄膜電晶體及記憶體元件

Micro-crystalline silicon thin film transistors and memory devices

凃政暉(Cheng-Hui Tu)

指導教授 ： 謝嘉民

國立交通大學/電機學院/光電工程系所/碩士(2012年)

https://doi.org/10.6842/NCTU.2012.00642

摘要

本論文利用感應耦合型電漿化學氣相沉積系統在265oC下製備高結晶性及低電阻率之微晶矽薄膜。藉由X光粉末繞射儀及電子束穿透顯微鏡分析驗證微晶矽薄膜具有高結晶性和極薄的非晶矽孵化層。此外，透過系統性的介電質參數最佳化，如氬流量、射頻功率、腔體壓力及甲烷/一氧化二氮的比例等，開發出高品質的介電層薄膜。利用高/低頻電容量測法萃取介面缺陷能態密度、漏電流及蝕刻率評估等方式驗證超薄(<5奈米)、低漏電流(10-8安培/平方公分於10伏特操作電壓下)且緻密的介電層。因此，利用此高品質的介電層，我們利用電將技術開發出超低漏電流低缺陷介電層並整合到不同厚度之薄膜電晶體，成功地將起始電壓降低了約1伏特。此電漿技術將可以達到製造3D堆疊元件的願景。整合此高結晶性及低缺陷之主動層及介電層的堆疊式上閘極和下閘極之微晶矽薄膜電晶體，其載子遷移率分別達到466和123平方公分/伏特-秒、次臨界擺幅為0.1~0.2 V/decade，開/關比為106已達世界級水準。非揮發性記憶體，例如:快閃式記憶體、EEPROMs不論在高密度記憶體、邏輯電路或是在微電路的應用，Si基板上已經是將當成熟，但在玻璃上因Tg溫度限制仍然相當困難因。我們應用此介電層及主動層技術於金屬-氧化物-氮化物-氧化物-多晶矽型非揮發性記憶體，成功壓低抹除和寫入電壓，並可在10-6脈衝寬度及有效打開記憶體特性，達到省電節省成本的目的產業上在可攜式平板電子產品可提高電池壽命。

關鍵字

電晶體 ； 記憶體 ； 微晶矽

並列摘要

In this thesis, high crystallinity and low resistivity of intrinsic and n-type microcrystalline silicon (μc-Si:H) thin films were deposited at 265oC by inductively coupled plasma chemical vapor deposition system (ICPCVD). The high crystallinity of μc-Si:H and thin incubation layer of amorphous silicon (a-Si) were examined by the analysis of X-Ray diffraction (XRD) and transmission electron microscope (TEM), respectively. In addition, after systematically optimizing the parameters of dielectric, such as Ar flow, RF power, chamber pressure and the ratio of SiH4/N2O, the high quality dielectric was developed. The dielectric with ultra-thin thickness (5nm), low leakage current dielectric (10-8A/cm2 within 10 V operation) and compact film were examined by interface trap state density by high/low frequency method, analysis of leakage current and etching rate evaluation. Therefore, we use plasma to developed low leakage current and defect and successfully construct a series of top-gate thin film transistors (TFTs) with different thickness. This plasma technology will be able to achieve the vision of the 3D stacking device. This dielectric with low interface trap states enables the reduction of threshold voltage of 1 V. By integration of active layer with high crystallinity and dielectric with high quality, the staggered top- and bottom- gate TFTs achieved mobility of 466 cm2/V-s and 123 cm2/V-s, sub-threshold swing of 0.1~0.2 V/decade and on/off ratio of 106. Nonvolatile memories such as flash memories and electrically erasable programmable read-only memories (EEPROMs) on silicon wafers have been extensively utilized in high-density memories, programmable logic, and microcontrollers. However, fabricating nonvolatile memory devices with favorable electrical characteristics on glass substrates is difficult because of the limit on the glass transition temperature (Tg) of glass substrates. Finally, we implement this dielectric and active layer technology in metal-oxide-nitride-oxide-semiconductor (MONOS) type nonvolatile memory (NVM), successfully reduce the program/erase voltage, and constructi low temperature SONOS-memory operated with low and fast programmable pulses. Since SOP technology is primarily used for portable electronics, low power consumption is a basic requirement to ensure a long battery life. This breakthrough not only reduces the cost of device fabrication but also is very promising for industrial application.

並列關鍵字

Thin film transistor ； Memory ； Micro-crystalline Silicon

參考文獻

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