製程參數對引洞成長之碳奈米管電阻的影響

Effect of process parameters on the resistance of carbon nanotube vias

王順武(Shun-wu Wang)

指導教授 ： 黃豐元

國立中央大學/工學院/機械工程學系/碩士(2007年)

摘要

本實驗利用IC製程中曝光微影的方式，在矽晶圓上定義出內連線(Interconnect)的引洞結構（Via），並且使用微波電漿化學氣相沉積系統（Microwave plasma chemical vapor deposition, MPCVD）從引洞結構中成長出碳奈米管(Carbon nanotube)，達到控制碳奈米管定位成長之目的，並且利用碳奈米管取代金屬導線作為內連線導線。製作內連線引洞結構時，分別設計在相同面積的範圍下，有單一引洞結構與陣列引洞結構並且使用三種不同金屬材料鈦（Ti）、鉭（Ta）與鋁（Al）作為下電極，最後沉積上電極金屬Ti、Ta或Al與碳奈米管連結形成二極體元件。再利用掃描式電子顯微鏡（SEM）、拉曼光譜儀（Raman spectroscopy）和I-V量測系統，分別探討在不同製程參數下，所成長之碳奈米管的形態與石墨化程度對其二極體元件電性的影響，並且比較三種不同下電極金屬（Ti、Ta與Al）在相同面積的範圍下，單一引洞與陣列引洞結構對二極體元件其電性的差異。
為了配合IC製程和鋁本身的融點，本實驗採用低溫製程，溫度從350 ℃到500 ℃，利用施加負偏壓來幫助碳管成長；由實驗結果發現碳奈米管的直徑隨著基板溫度與負偏壓的增加而逐漸減小；而且隨著基板溫度與施加負偏壓的增加，實驗中所成長的碳奈米管石墨化程度有逐漸增加的趨勢，元件的電阻值也較低。在相同面積下，陣列引洞結構之元件的電阻值，比單一引洞結構之元件的電阻值還小；而且在相同的製程參數下，以Ti為二極體元件的下電極時，其電阻值比Ta或Al為下電極時所量測到的電阻值還小；本實驗還採用不同的上電極材料Ti、Ta和Al做比較，上電極為Ti時，其電阻值和Ta差不多，但是比Al為上電極所量測到的電阻值還小。因此，本實驗中以Ta為上電極，Ti為下電極，基板溫度為500 ℃，前處理電漿功率為1200 W，前處理時間5 min，成長電漿功率為1200 W，成長時間15 min，甲烷氣體流量比例為30 %、負偏壓為200 V時，所成長的碳奈米管其石墨化程度最好（38 %），並且量測到其二極體元件的電阻值也是最低（71Ω）。

關鍵字

內連線 ； 碳奈米管 ； 引洞結構 ； 電阻

並列摘要

This research is using integrated-circuit（IC）photolithography to manufacture the structure of interconnect via in silicon wafer. We use microwave plasma chemical vapor deposition（MPCVD）to grow carbon nanotubes（CNTs）in the via to control the growth of vertically in-situ carbon nanotubes and achieve replacing the metal in the via with CNTs. We design a single-via and array-via in the same region with three different metals（Ti, Ta and Al）bottom electrode. Finally, we deposit the top electrode with Ti, Ta or Al to connect with CNTs to form CNT diode structure. Then we use SEM, Raman spectroscopy, and I-V system to analysis diode structure. We discuss the effect of process parameters on the properties and the diode resistances of CNTs in single and array via, and compare the conductive performance of diode with Ti , Ta and Al bottom electrode.
This research is using low temperature manufacture to match up the IC manufacture and aluminum melting point. The temperature which we selected from 350℃ to 500 ℃ and we use bias to increase the growth of CNTs. From the result, We find that multi-wall carbon nanotube（MWNT） diameter decreases with increase of substrate temperature and bias; and the degree of graphitization of MWNTs increases with the increase of substrate temperature and bias. Consequently, the diode resistance of MWNTs in both single and array vias decreases with the increase of MWNT graphitization. In the same via region, the MWNT diode resistances of the array vias are lower than those of the single vias; the MWNT diode resistances with the Ti bottom electrode are lower than those with the Ta or Al bottom electrode. And we also select diffecent top electrode with Ti, Ta and Al, and then compare it. The diode resistance with Ti top electrode are almose the same with Ta top electrode and lower with Al top electode. Thus, in this research we use Ta top electode and Ti bottom electode, PP: 1200 W, PG: 1200 W, Temp. : 500 ℃, CH4 flow ratio: 30%, and bias: 200 Volt, we measure the best degree of graphitization (38%) and the lowest MWNT diode resistance (71 Ω).

並列關鍵字

integrated-circuit（IC） ； resistance ； via ； interconnect ； carbon nanotubes

參考文獻

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