採用無負載及切換式運算放大器共享技術之一伏特十位元10MSample/s管線式類比數位轉換器

A 1-V, 10BIT, 10MSAMPLE/S SWITCHED-OPAMP PIPELINED ADC USING LOADING-FREE AND OPAMP-SHARING TECHNIQUES

陳信宇(Hsin-Yu Chen)

指導教授 ： 黃淑絹

大同大學/電機資訊學院/電機工程學系所/碩士(2008年)

摘要

本篇論文主要描述一個低功率、10位元、操作頻率在10MHz而工作電壓在1V的管流式類比數位轉換器之設計，並提出利用切換式運算放大器共享技術搭配無負載技術來減少轉換器元件數量。有別於一般的低功率低電壓電路，本架構不需要過多的運算放大器以及電容，單純利用開關切換達到無負載以及運算放大器共用。本轉換器採用標準0.18um 1P6M CMOS製程，並透過Hspice模擬電路架構，本轉換器操作在10MHz的取樣頻率，工作電壓為1V，輸入頻率為595kHz下最大SNDR為55.13dB，其總功率消耗為19mW，佈局面積約為1.38mm×1.38mm，完整的測試報告將由日後提出。

關鍵字

管線式類比數位轉換器 ； 切換式運算放大器 ； 運算放大器共享 ； 無負載技術

並列摘要

In this thesis, a 10-bit 10-MHz pipelined analog-to-digital converter (ADC) consisted of 1.5-bit/stage has been designed and implemented in TSMC 0.18-µm 1P6M CMOS process. In order to operate at 1 V, the pipelined analog-to-digital converter uses switched-opamp technique. In addition, this thesis proposes a novel pipelined stage by combining the opamp-sharing and loading-free techniques to reduce the power consumption. An opamp with two output stages is employed to merge opamp-sharing and switched-opamp structures. The passive sample-and-hold (S/H) replaces the conventional sample-and-hold circuit to save power. This work only needs five opamps in the pipelined ADC. Therefore, the proposed pipelined ADC can operate under low power supply and reduce the total power consumption. The ADC has been simulated by HSPICE. The resulting peak signal-to-noise and distortion ratio (SNDR) of the pipelined ADC is 55.13 dB with sampling frequency of 10 MHz at input frequency of 595 kHz. Power consumption of this ADC is 19mW with 1V power supply. The chip area of this pipelined ADC is 1.38mm×1.38mm without digital error correction. The measurement results will be reported later.

並列關鍵字

pipelined ADC ； switched-opamp ； opamp-sharing ； loading-free

參考文獻

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