利用一新式電容放大技巧之展頻時脈產生器設計與製作

郭仲宇

doi:10.6342/NTU.2009.00520

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利用一新式電容放大技巧之展頻時脈產生器設計與製作

The Design and Implementation of Spread Spectrum Clock Generators Using a Novel Capacitance Multiplication Method

郭仲宇 , Masters　　Advisor：盧奕璋　　

英文 DOI： 10.6342/NTU.2009.00520

電磁輻射干擾；展頻時脈產生器；鎖相迴路；壓控震盪器；迴路濾波器； Electromagnetic interference (EMI) ； Spread spectrum clock generator (SSCG), Phase locked loop (PLL) ； Voltage controlled oscillator (VCO) ； Low pass filter (LPF)

Abstract │ Reference (49) │ Altmetrics

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Electronic components often generate radiated electromagnetic interference (EMI)that affects the operations of nearby components. It becomes a serious problem that faster operating speeds result in more EMI. It has been proved that the spread spectrum clocking can reduce the peak power into a controllable range, thus achieving EMI reduction effectively. A spread spectrum clock generator (SSCG) is a phase locked loop (PLL) with appropriate frequency-modulated output. One of the
implemental methods involves direct modulation of the voltage controlled oscillator (VCO) in PLL. But the
loop bandwidth should be much smaller than the modulation frequency to allow frequency variation; i.e. there should be large passive components, especially capacitors as using this method. Similarly, the small bandwidth is also required for stability when a small input reference is applied to a PLL. In this thesis, a modified dual-path loop filter is presented. This configuration can have a multiplication ratio more than n. This configuration is applied to the SSCG as well.
  Chapter 1 gives a brief summary of the PLL, including its applications, linear model, related noise source, and issues among each block.
  Chapter 2 focuses on the basic properties of SSCG, different profiles on the spectrum, timing impacts within spread spectrum, and summarizes the circuit implementation methods of the SSCG.
  Chapter 3 provides a technique for capacitance multiplication utilized in the low pass filter (LPF). We will give a detailed description and compare the proposed one with the previous work using Simulink simulator.
  In chapter 4, an SSCG with direct modulation on VCO and based on the technique mentioned in chapter 3 is presented, fabricated in 0.18-μm TSMC CMOS process. The
experimental results of this chip are also presented. The experimental results also confirm that different modulation profiles result in different EMI reduction.
  Chapter 5 implements another SSCG used for X-band application. A simple feedback compensation mechanism added in the original charge pump is presented. The
sections contain the circuit descriptions of each building block and list some cautions when layout and designing.
  We also leave some conclusions and recommendations for future work at the end of this thesis.

Reference ( 49 ) 〈TOP〉

[1] G. -Y. Tak, S.-B. Hyun, T. Y. Kang, B. G. Choi and S. S. Park, “A 6.3GHz-9GHz CMOS fast settling PLL for MB-OFDM UWB application,” IEEE J. Solid-State Circuits, vol.40, no.8, Aug, 2005, pp. 1671-1679.
連結：
[2] Y. Koo, H. Huh, Y. Cho, J. Lee, J. Park, K. Lee, D. -K. Jeong and W. Kim, ”A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS and celluar CDMA wireless
連結：
[3] D. Mukherjee, J. Bhattacharjee and J. Laskar,” A differentially-tuned CMOS LC VCO for low-voltage full-rate 10 Gb/s CDR circuit,” IEEE Microwave Symposium Digest, vol. 2, June 2002, pp. 707-710.
連結：
[4] M. Ramezani, C. Andre and T. Salama,"A 10Gb/s CDR with a half-rate bang-bang phase detector,” IEEE International Symposium on Circuits and Systems, ISCAS, May 2003, pp181-184
連結：
[5] Z.O. Gursoy and Y. Leblebici,"Design and realization of a 2.4 Gbps - 3.2 Gbps clock and data recovery circuit using deep-submicron digital CMOS technology,"IEEE SOC Conference, Sept. 2003, pp. 99-102.
連結：

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