DOI
stands for Digital Object Identifier
(
D
igital
O
bject
I
dentifier
)
,
and is the unique identifier for objects on the internet. It can be used to create persistent link and to cite articles.
Using DOI as a persistent link
To create a persistent link, add「http://dx.doi.org/」
「
http://dx.doi.org/
」
before a DOI.
For instance, if the DOI of an article is
10.5297/ser.1201.002
, you can link persistently to the article by entering the following link in your browser:
http://dx.doi.org/
10.5297/ser.1201.002
。
The DOI link will always direct you to the most updated article page no matter how the publisher changes the document's position, avoiding errors when engaging in important research.
Cite a document with DOI
When citing references, you should also cite the DOI if the article has one. If your citation guideline does not include DOIs, you may cite the DOI link.
DOIs allow accurate citations, improve academic contents connections, and allow users to gain better experience across different platforms. Currently, there are more than 70 million DOIs registered for academic contents. If you want to understand more about DOI, please visit airiti DOI Registration ( doi.airiti.com ) 。
郭仲宇 , Masters Advisor:盧奕璋
英文
DOI:
10.6342/NTU.2009.00520
電磁輻射干擾 ; 展頻時脈產生器 ; 鎖相迴路 ; 壓控震盪器 ; 迴路濾波器 ; Electromagnetic interference (EMI) ; Spread spectrum clock generator (SSCG), Phase locked loop (PLL) ; Voltage controlled oscillator (VCO) ; Low pass filter (LPF)


- [1] G. -Y. Tak, S.-B. Hyun, T. Y. Kang, B. G. Choi and S. S. Park, “A 6.3GHz-9GHz CMOS fast settling PLL for MB-OFDM UWB application,” IEEE J. Solid-State Circuits, vol.40, no.8, Aug, 2005, pp. 1671-1679.
連結: - [2] Y. Koo, H. Huh, Y. Cho, J. Lee, J. Park, K. Lee, D. -K. Jeong and W. Kim, ”A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS and celluar CDMA wireless
連結: - [3] D. Mukherjee, J. Bhattacharjee and J. Laskar,” A differentially-tuned CMOS LC VCO for low-voltage full-rate 10 Gb/s CDR circuit,” IEEE Microwave Symposium Digest, vol. 2, June 2002, pp. 707-710.
連結: - [4] M. Ramezani, C. Andre and T. Salama,"A 10Gb/s CDR with a half-rate bang-bang phase detector,” IEEE International Symposium on Circuits and Systems, ISCAS, May 2003, pp181-184
連結: - [5] Z.O. Gursoy and Y. Leblebici,"Design and realization of a 2.4 Gbps - 3.2 Gbps clock and data recovery circuit using deep-submicron digital CMOS technology,"IEEE SOC Conference, Sept. 2003, pp. 99-102.
連結: