利用一新式電容放大技巧之展頻時脈產生器設計與製作

The Design and Implementation of Spread Spectrum Clock Generators Using a Novel Capacitance Multiplication Method

郭仲宇(Chung-Yui Kuo)

指導教授 ： 盧奕璋

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.00520

摘要

電子產品容易對周遭零件產生電磁輻射干擾(EMI)，隨著電路操作速度越來越快，其影響越甚，展頻技術是一解決此問題的有效方法，一建構在對鎖相迴路中的壓控震盪器直接調變的機制以達到展頻效果之方法被提出，然而此方法中對迴路頻寬的要求必須遠小於調變訊號頻率，換句話說，在電路實作上，必須利用相當大的被動電容，在此論文中，亦提出一電容放大技巧來解決此問題。
第一章簡單摘要鎖相迴路，包括其線性模型，雜訊源，和各組成區塊設計時所應注意事項。
第二章主要在介紹展頻時脈產生器之基本觀念，包含基本原理，調變頻率、調變輪廓和展頻量之間的關係，以及展頻對於時脈在時域下的影響，最後摘要介紹四種電路實現的方法。
第三章介紹提出之雙迴路電容放大技巧，並與相關文獻作一整理比較。
第四章提出一展頻時脈產生器，其調變路徑直接對壓控震盪器作用達到展頻效果，此章節包含行為模擬與系統分析，所提出之架構利用TSMC 0.18μm 1P6M CMOS製程製作，量測結果並於最後呈現。
第五章實作另一操作於X-band 應用中的展頻時脈產生器，並提出一對充電汞之補償機制，以增加其電流匹配程度。

關鍵字

電磁輻射干擾 ； 展頻時脈產生器 ； 鎖相迴路 ； 壓控震盪器 ； 迴路濾波器

並列摘要

Electronic components often generate radiated electromagnetic interference (EMI)that affects the operations of nearby components. It becomes a serious problem that faster operating speeds result in more EMI. It has been proved that the spread spectrum clocking can reduce the peak power into a controllable range, thus achieving EMI reduction effectively. A spread spectrum clock generator (SSCG) is a phase locked loop (PLL) with appropriate frequency-modulated output. One of the
implemental methods involves direct modulation of the voltage controlled oscillator (VCO) in PLL. But the
loop bandwidth should be much smaller than the modulation frequency to allow frequency variation; i.e. there should be large passive components, especially capacitors as using this method. Similarly, the small bandwidth is also required for stability when a small input reference is applied to a PLL. In this thesis, a modified dual-path loop filter is presented. This configuration can have a multiplication ratio more than n. This configuration is applied to the SSCG as well.
Chapter 1 gives a brief summary of the PLL, including its applications, linear model, related noise source, and issues among each block.
Chapter 2 focuses on the basic properties of SSCG, different profiles on the spectrum, timing impacts within spread spectrum, and summarizes the circuit implementation methods of the SSCG.
Chapter 3 provides a technique for capacitance multiplication utilized in the low pass filter (LPF). We will give a detailed description and compare the proposed one with the previous work using Simulink simulator.
In chapter 4, an SSCG with direct modulation on VCO and based on the technique mentioned in chapter 3 is presented, fabricated in 0.18-μm TSMC CMOS process. The
experimental results of this chip are also presented. The experimental results also confirm that different modulation profiles result in different EMI reduction.
Chapter 5 implements another SSCG used for X-band application. A simple feedback compensation mechanism added in the original charge pump is presented. The
sections contain the circuit descriptions of each building block and list some cautions when layout and designing.
We also leave some conclusions and recommendations for future work at the end of this thesis.

並列關鍵字

Electromagnetic interference (EMI) ； Spread spectrum clock generator (SSCG), Phase locked loop (PLL) ； Voltage controlled oscillator (VCO) ； Low pass filter (LPF)

參考文獻

[30] S. –H. Li, S. –L Jang, Y. –S. Chang and C. F. Li, “A New LC-tank Voltage Controlled Oscillator” IEEE Asia-Pacific Conference on Circuits and Systems, Dec.2004, pp.425-427.

[1] G. -Y. Tak, S.-B. Hyun, T. Y. Kang, B. G. Choi and S. S. Park, “A 6.3GHz-9GHz CMOS fast settling PLL for MB-OFDM UWB application,” IEEE J. Solid-State Circuits, vol.40, no.8, Aug, 2005, pp. 1671-1679.

[2] Y. Koo, H. Huh, Y. Cho, J. Lee, J. Park, K. Lee, D. -K. Jeong and W. Kim, ”A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS and celluar CDMA wireless

[3] D. Mukherjee, J. Bhattacharjee and J. Laskar,” A differentially-tuned CMOS LC VCO for low-voltage full-rate 10 Gb/s CDR circuit,” IEEE Microwave Symposium Digest, vol. 2, June 2002, pp. 707-710.

[4] M. Ramezani, C. Andre and T. Salama,"A 10Gb/s CDR with a half-rate bang-bang phase detector,” IEEE International Symposium on Circuits and Systems, ISCAS, May 2003, pp181-184