存在於互補式金氧半電感電容式振盪器之相位雜訊對偏壓電流依賴度之分析

在無線通訊系統中，本地振盪源扮演了一個很重要的角色。其中本地振盪源通常是由一個頻率合成器所實現，以確保有穩定以及精確的頻率輸出。進一步地，在大部分的應用中，頻率合成器之相位雜訊嚴重地影響了整個傳送接收機之雜訊效能。身為一個在頻率合成器中之重要電路，壓控振盪器的雜訊將主宰在熱雜訊頻帶之相位雜訊。因此，為了使設計者對於相位雜訊有更進一步的理解，更深入的理論定性分析是必要的。本論文主要研究方向在探討相位雜訊對偏壓電流依賴度之關係。針對一個電感電容式之壓控振盪器，其主宰的雜訊源主要來自電感之等效並聯電阻、閘極之寄生電阻、金氧半電晶體、以及偏壓電路。當相位雜訊被不同之雜訊源所主宰，相位雜訊對偏壓電流依賴度將會有所不同。另外，本論文提出了一個簡潔的相位雜訊公式，用來支持本論文的定性分析。針對一些給定的系統參數，此相位雜訊之公式也可初步預測電感與電晶體所需要的設計參數與尺寸。相位雜訊對偏壓電流依賴度之分析是以一個5.4兆赫茲的電感電容式之壓控振盪器所實現。經由此顆使用台積電0.18深次微米製程之壓控振盪器，相關量測結果顯示相位雜訊確實與偏壓電流有性質上的關聯。當然，量測結果也將連帶與模擬結果以及理論模型曲線一起比較。最後，包含ESD防護電路，整個晶片所耗面積為1320 x 1190 um^2。

關鍵字

振盪器；元件雜訊；相位雜訊

並列摘要

In wireless communication systems, the local oscillator (LO) plays an important role. The local oscillator is usually realized as a frequency synthesizer so as to achieve the stable as well as precise oscillation frequency. Further, phase noise of a frequency synthesizer significantly affects the noise performance of the whole transceiver. In a PLL-based frequency synthesizer, VCO phase noise often dominates PLL phase noise in the 1/f^2 regime. Thus, deeper theoretical analysis is essential to give an objective insight. In this thesis, the relationship between phase noise and bias current is discussed. Noise contributors in a LC-tank oscillator are primarily composed of inductor noise, gate-resistor noise, noise from cross-coupled transistors, and noise from bias circuitry. In a word, tendencies of phase noise vs. bias current will be different due to different noise dominators. More details are discussed in the thesis. In addition, a compact phase noise formula in the 1/f^2 regime for single- and double-switching oscillators is proposed to support qualitative analyses of phase noise. For some given system specifications, like phase noise and power consumption, the sizing prediction can be initially obtained by this compact phase noise formula. These concepts are realized by the design of a 5.4-GHz CMOS LC-tank P-core VCO. Fabricated in TSMC 0.18-um CMOS mixed-signal process, related measured results are compared with simulation results and theoretical modeling curves to make several conclusions. Finally, the chip including ESD-PADs occupies an area of 1320 x 1190 um^2.

並列關鍵字

Oscillator ； Device Noise ； Phase Noise

參考文獻

[19] TSMC 0.35-μm Mixed Signal 2P4M POLYCIDE 3.3V/5V Spice Model, Document Number: T-035-MM-SP-002, Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan, R.O.C., June 2007.

[20] TSMC 0.35-μm POLYCIDE (5V) MOS Transistor Noise Data, Document Number: TA-1095-6303, Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, Taiwan, R.O.C., June 1998.

[51] T. H. Lee and Ali Hajimiri, “Oscillator Phase Noise: A Tutorial,” IEEE Journal of Solid-State Circuits, vol. 35, no. 3, pp. 326-336, March 2000.

[85] Neric H. W. Fong, Jean-Olivier Plouchart, Noah Zamdmer, Duixian Liu, L. F. Wagner, Calvin Plett, and N. Garry Tarr, “Design of Wide-Band CMOS VCO for Multiband Wireless LAN Applications,” IEEE Journal of Solid-State Circuits, vol. 38, no. 8, pp. 1333-1342, Aug. 2003.

[4] Jim Koeppe and Ramesh Jarjani, ”Enhanced Analytic Noise Modeling for RF CMOS Design,” IEEE Custom Integrated Circuits Conference, pp. 383-386, Sep. 2004.

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存在於互補式金氧半電感電容式振盪器之相位雜訊對偏壓電流依賴度之分析

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