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  • 學位論文

以FPGA實現超音波原始資料的解調及無失真壓縮

Implementation of Ultrasonic Raw Data Demodulation and Lossless Compression Using FPGA

指導教授 : 李百祺

摘要


本研究主旨為在FPGA上實現超音波原始資料的解調及壓縮,利用硬體的計算能力突破傳輸介面的瓶頸,有效降低軟體基礎的超音波影像系統中,即時成像時的高頻寬需求。傳統的超音波影像系統以硬體系統為主,利用其高度平行化架構達成在短時間內處理陣列系統即時成像所需的龐大資料量。然而隨著電腦科技發展,無論是處理器時脈、傳輸介面頻寬、抑或平行運算能力都有長足進步,以軟體系統取代硬體數位電路不再是無稽之談。相較於硬體系統,軟體系統在開發、更新、整合時所需的成本遠低於硬體,並且能以相同的硬體架構達成更多元化的功能。因此,以軟體為基礎的影像系統便成為近年來的發展趨勢。以軟體為基礎的系統縱然有著許多優點,但其所需的大量資料傳輸亦會成為系統即時成像的瓶頸所在。本研究提出以前端硬體電路中原用來控制系統訊號的FPGA為標的,在其上實行超音波原始資料的基頻解調及無失真壓縮,以有效降低所需的資料傳輸量。運用FPGA所具有的可程式化特性及豐富硬體電路資源,以額外增加的運算來換取軟體系統中頻寬需求的降低。在基頻解調的部分,本研究利用對象系統中,取樣頻率為探頭中心頻率四倍的特性,以及Xilinx FPGA上提供的DSP元件進行濾波所需的摺積運算,可減少解調時的資源使用量並同時將架構簡化。解調過程中,原始資料會先轉換為IQ資料使資料量增為兩倍,再經過縮減取樣後變為四分之一,共提供兩倍的壓縮率。在壓縮的部分,本研究提出一可變長度編碼方法進行無失真壓縮,其輸出包含一可變長度之編碼字串及一固定長度之位址資訊。此位址資訊使解碼方能以平行化架構進行解碼,可與後端軟體系統中的平行運算技術,如NVIDIA的CUDA架構相互配合,以提升整體運算效率。本壓縮方法可提供約1.5~1.7倍的壓縮率,與解調結合後可達到整體約3~3.4倍的壓縮效果。在128通道系統、每幅189條波束、每條波束取樣深度2048點的扇形掃描中,若要實現每秒30幅的即時成像,所需的傳輸頻寬為2.77GB/s。以現行PCI-E 2.0介面每個通道500MB/s的最大傳輸率而言,需使用8通道的PCI-E 2.0介面卡(4GB/s)才能負擔。若使用本研究提出的即時壓縮方法,可將頻寬降低3倍以上,使用2通道的PCI-E介面卡(1GB/s)即可負擔傳輸量。

並列摘要


As compared with conventional hardware-based ultrasonic imaging systems, a software-based system provides the advantages of low development cost and system programmability. Therefore, software-based systems have become the trend of ultrasound system development. Despite of the advantages, massive data transmission becomes one of the bottlenecks to perform real-time software based imaging. It is the purpose of this research to develop and implement efficient methods for real-time data compression of ultrasound RF data with a field programmable gate array (FPGA) device. In the proposed methods, the data size is reduced by performing base-band demodulation and lossless compression on the FPGA in front-end systems. In other words, by taking advantages of the computation power in the front-end, the large transmission bandwidth requirement for real-time software-based beam forming can be mitigated. The total compression ratio reaches to about 3.4 without introducing any loss to the data. In a 128-channel array system with 189 beams per frame, 2048 points per beam, the hardware bandwidth for performing real-time imaging requires 2.77GB/s. This requires a PCI-E 2.0 x8 protocol to run at full speed (4GB/s, with 500MB/s per lane). With the proposed method, the bandwidth requirement can be reduced to one-third of the original requirement. Therefore, only a PCI-E 2.0 x2 protocol is required.

參考文獻


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