透過您的圖書館登入
IP:3.12.36.65
  • 學位論文

使用圖形介面實行超大型積體電路時脈檢測和工程變更命令的實行

VLSI Timing Visualization Plus ECO

指導教授 : 陳中平

摘要


在今日高效能且低功率的晶片趨勢下,電路最佳化軟體成了重要的課題。而其中,最佳化軟體不只要探討電路中時間的延遲、功率的消耗和面積的大小。 在本篇研究中,我們的目的是要使電路設計者能縮減掉許多檢測時間延遲的時間。過去,電路設計者往往使用文字介面的檢測軟體,雖然這些商用最佳化軟體在經過強大且精密的計算後,能給設計者一個很理想的答案。但設計者在看到僅有文字的時間報告結果後,往往要花許多時間去更改電路的形式。所以我們希望電路設計者能在檢驗時能觀察到電路的樣子,如此一來,設計者不僅能輕鬆更改時間關鍵路線上的邏輯閘,甚至可以簡單觀察並更改關鍵邏輯閘附近的邏輯閘。而其中,我們為了做電路圖形介面,我們也設計了如何使線路交叉數減至最少的演算法,使設計者可以更清楚的觀察電路的樣子。 而在使用設計者人為調整的方法我們稱為工程變更命令,此方法主要是使設計者不需要等待一而再再而三的最佳化合成,因為如此往往所得到的結果會收斂到一個狀態,但仍然不是設計者希望的。所以在經過設計者本人使用圖形介面調整的情況下,必可以得到設計者需要的電路結果,更重要的,也可以節省很多的時間。

並列摘要


Circuit optimization is a very important step in high performance and low power IC design. It has a significant impact on its delay, power dissipation and area of the final circuit. The goal of our tool is to let VLSI designers easily repair timing violation problems. We can easily view the circuit by combining the RTL code that is after synthesised and the timing report from Primetime. We can show designer the critical path, to make sure whether it is what the designer expect. If it’s the same, then congratulation, the designer get a great circuit after synthesised. But if not,then designer can see what happened. The designer can see, which gate makes the critical path differ from he expected. Then the designer can click the toolbar icon to change the type of gate ( because different type of the same gate have different sizes.) After that, we can response the designer a new RTL code with the gate type changed. Use the new RTL code to run Primetime again, and use the tool to open those two new files. If the designer well changed the type of gate, then the designer will see the different critical path to the previous one. After the steps above, the designer can finally get a well timing circuit they expect.

參考文獻


[2] Jasmin Blanchette and Mark Summerfield, “C++ GUI Programming with Qt 4, Second Edition,” Prentice Hall, USA, 2008.
[3] Sadiq M. Sait and Habib Youssef , “VLSI Physical Design Automation,” World Scientific, Singapore, USA and UK, 2004.
[5] George Michael, “PrimeTime Static Timing Analysis Tool”, Fall, 2006.
[6] Markus Eiglsperger and Martin Siebenhaller and Michael Kaufmann, “An Efficient Implementation of Sugiyama’s Algorithm for Layered Graph Drawing”, Journal of Graph Algorithms and Applications, vol.9, no.3, pp.305-325, 2005.
[1] Sachin Sapatnekar, “Timing,” Kluwer Academic Publishers, USA, 2004.

延伸閱讀