基於電流控制震盪器二階連續時間三角積分器設計

Design of a Current-Controlled Oscillator-Based 2nd-order Continuous-Time Delta-Sigma Modulator

謝承佑(Cheng-Yu Hsieh)

指導教授 ： 林宗賢

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2021年)

https://doi.org/10.6342/NTU202100099

摘要

本論文著重探討應用於物聯網感測系統之類比數位轉換器電路設計，此電路的主要任務為將振幅小且低頻的信號直接轉換為數位訊號，同時維持訊號的完整度。但由於電路的直流偏移、閃爍雜訊都落在低頻帶的範圍，因此訊號的品質容易受影響，也增加了設計難度。本篇採用環形震盪器作為積分器的連續時間三角積分轉換器，希望在維持低功耗以及低面積同時維持良好的精確度。
本論文對我們所設計的二階連續時間三角積分轉換器做了實作及量測，此電路實作於台積電180奈米製程。為了能夠適應製程演進與物聯網低功耗的需求，我們將供應電壓降為1.2 Ｖ。在低電壓操作的要求之下，我們利用環形震盪器取代類比積分器，以實現感測器電路。這個晶片的設計為將第一級積分過的訊號藉由第二級由環形震盪器所構成的量化器做量化，由於量化器本身具有一階三角積分調變的特性，故整個迴路會有兩階的三角積分調變，且此量化器的數位輸出為一個經動態單元匹配後的訊號，其可以提升數位類比轉換器的線性度，故不需要再加上傳統的動態權重平均電路，而能有較大的頻寬。
此晶片使用1.2 V作為供應電壓，功率消耗為26.2 μW。在160 nAPP的輸入以及2 kHz的頻寬下，可以達到60 dB的信噪比。在品質因素方面達到FoMs = 136.9 dB及FoMw = 10.09 pJ/conv，晶片面積為0.22 mm2。

關鍵字

低功率 ； 低雜訊 ； 感測器 ； 類比前端電路 ； 環形震盪器 ； 類比數位轉換器

並列摘要

In this thesis, we will discuss the design of an analog-to-digital converter (ADC) which converts the weak and low-frequency analog signal into digital signal for internet of things (IoT) sensor applications while maintains signal integrity. Since the signal, offset and flicker noise are all in the low-frequency range, the signal is susceptible to these non-idealities and increases the design challenge. The ring oscillator-based integrator is applied to construct continuous-time delta-sigma modulator (CTDSM) to maintain good resolution with the low-power and low-area requirement.
This thesis includes the implemented and measured CTDSM designed and fabricated in TSMC 180 nm. The supply voltage is reduced to 1.2V in order to meet the requirement of low power consumption of the IoT. Under the low voltage operation, a ring oscillator is used instead of an analog integrator to implement a sensor circuit. The CTDSM signal would be integrated and enter into the second stage, which is a CCO with phase-to-digital converter as a quantizer.
Due to the first-order noise shaping characteristic of the second stage, the whole loop shows second-order noise shaping. The second stage quantize the signal as a digital thermometer code with dynamic element matching (DEM). Comparing with prior art of dynamic weighted averaging (DWA) circuit, this automatic DEM technique can benefit from bigger bandwidth. The core area of the circuit is 0.22 mm2. The SNR is 60 dB (with the bandwidth of 2 kHz) under 160 nAPP input signal. The figure of merits (FoM) FoMs equals to 136.9 dB and FoMw is 10.09 pJ/conv.

並列關鍵字

Low-Power ； Low-Noise ； Sensor ； Analog Front-End (AFE) ； Ring Oscillator ； Analog to Digital Converter (ADC)

參考文獻

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