連續時間增量型三角積分調變器

Continuous-Time Incremental Delta Sigma Data Converter

王鼎洋(Ting-Yang Wang)

指導教授 ： 李泰成

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.02718

摘要

增量型三角積分調變器有許多應用，如直流測量，線腳測量，生物醫學應用測量，感測器陣列測量，或適用於任何多通道測量應用。大多數增量型三角積分調變器是由離散時間結構來實現。但在三角積分調變器中有另一種結構為連續時間結構，其耗能比離散時間結構要少得多。原因為連續時間結構不像離散時間結構要需要很大的運算放大器建立時間。本文使用的連續時間結構，使調變器速度更快，功耗更低。本文提出三階三位元，過採樣率為64的連續時間增量型三角積分調變器，使用台積電1P6M T18製成。本晶片操作於一百兆赫茲取樣頻率，並於七百三十七千赫茲的有效頻寬下得到73.82 dB的訊號雜訊失真比。在3.3伏特的電源供應下總共消耗6.6毫安培，晶片的核心面積小於0.25平方毫米。

關鍵字

增量型三角積分調變器 ； 離散時間 ； 連續時間

並列摘要

Incremental sigma-delta data converter (IDC) has many useful applications such as DC measurement, linear feet measurement, biomedical application, sensor array application, and is suitable for any multi-channel applications. Most of the IDC today is made by discrete-time (DT) structure. But continuous-time (CT) structure consumes much less power than DT one, since continuous ramping instead of discrete settling behavior is involved in CT loop-filters. This thesis use CT structure to make the modulator faster and consume less power. A third order 3-bit CT-IDC with OSR=64 fabricated in TSMC T18 1P6M technology is proposed in the thesis. The modulator is operated at 100MHz sampling clock. It achieves peak SNDR of 73.82dB within 737 kHz bandwidth. This chip dissipates 6.6 mA from a 3.3V supply. The core area of this modulator occupies smaller than 0.25mm2.

並列關鍵字

incremental sigma-delta data converter ； discrete-time ； continuous-time

參考文獻

[3] M. Mollazadeh, K. Murari, G. Cauwenberghs, and N. Thakor, “Micropower CMOS-integrated low-noise amplification, filtering, and digitization of multimodal neuropotentials,” IEEE Trans. Biomed. Circuits Syst., vol. 3, no. 1, pp. 1–10, Feb. 2009.

[4] Y. M. Chi and G. Cauwenberghs, “Micropower integrated bioamplifier and auto-ranging ADC for wireless and implantable medical instrumentation,” in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), 2010, pp. 334–337.

[5] B. Razavi, Principles of data conversion system design, Wiley-IEEE Press, New York, 1995.

[8] J. A. Cherry and W. M. Snelgrove, “Excess loop delay in continuous time delta-sigma modulators,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 4, pp. 376–389, Apr. 1999.

[9] G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and E. Romani, “A 20-mW 640-MHz CMOS continuous-time ΣΔ ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2641–2649, Dec. 2004.