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  • 學位論文

數位電視系統核心晶片設計之研究

THE STUDY OF DIGITAL TV SYSTEM CORE DESIGN AND IMPLEMENTATION

指導教授 : 陳良基

摘要


這份論文提出了數位電視系統的四個視訊核心技術。分別為MPEG2視訊解碼器,NTSC/PAL視訊解碼器,去交錯視訊處理器,及低必v濾波器設計。 MPEG2視訊解碼器在數位電視系統中,運算量是最大的一塊。一個專屬的加速器就是為了解決這樣的問題。利用了管線,平行處理的技巧,提高硬體執行效率,降低時脈頻率。針對特定弁鈰竣ぞ畦H減少硬體成本。在晶片設計的流程中,HDL模擬也是一大問題,以往總是要用大量的Pattern來做測試。這樣子非常的耗時。在這兒針對MPEG2 視訊解碼器提出了一個測試Pattern,可以減省大量測試的時間。 NTSC/PAL Video Decoder介於類比與數位電路之間,因此佔了一個非常重要的角色。提出的架構及演算法列於論文的第二部分。此部分包含了類比前級電路,全數位Line-lock,3D-adaptive Y/C分離,Burst鎖相迴路,及Demodulator。整個系統僅需要單一時脈27MHz振盪器,除了ADC及前級類比電路之外,皆採用全數位方式實現。 論文第三部分則是循序式掃描的硬體設計,用於將傳統交錯式掃描的視訊轉成循序式掃描的格式。此循序式掃描硬體為Motion adaptive的方式,內部有包含了ELA median方向性的內插,同位性四圖場水平移動偵測。提出的演算法符合低成本低複雜性的考量,並兼具快速處理的能力。由實驗結果可以看出提出的方法優於目前市面的去交錯處理器。 一般的無線手持系統中,Filter佔了一個很重要的角色。它通常是用來影像視訊及通訊相關的訊號處理。而一般的應用都是給定一個特定的規格,設計出一個專門的濾波器較符合成本效益。在最後一章節,提出了低必v濾波器的設計方法。此方法可以實現於direct form的濾波器中並且降低很大量的Power。 提出的四種技術可以改善視訊的品質且非常適合整合於即時的數位電視系統中。

關鍵字

濾波器 去交錯 數位電視 晶片

並列摘要


This dissertation presents four video processing techniques that are essential for real-time digital TV systems. The MPEG2 video decoder is the most computationally intensive part of a digital TV system. A dedicated accelerator is usually designed for solve this problem. However simulation on EDA tool platform is very time-consuming, that is not corresponded to the concept of time to market. In the first part of this dissertation, a fully pipeline MPEG2 video decoder architecture and an efficient test bitstream design methodology are presented. Each necessary function is selected and the corresponding symbols are inserted into bitstream in the macroblock level; rearrange these macroblock distributions for reducing the macroblocks numbers. It takes about 7 hours to simulate a full functionality of MPEG2 video decoder at RTL deign stage on the Ultrasparc-IITM 360Mhz CPU, which is 50 times faster than using those conformance bitstreams. Video decoder is always necessary, if the analog video still exist in the world. Proposed architecture of Video Decoder is presented in the second part. It consists of the analog front-end, All Digital Line Lock, 3D Adaptive Y/C Separator, Burst PLL, and Demodulator. Jitter effect could be eliminated when All Digital Line Lock is adopted. The 3D adaptive comb filter improves the video quality of Y/C Separation. Burst PLL could lock sine wave both in 3.58 MHz and 4.43 MHz for demodulating the accurate chrominance signal. Single clock system and fully digital design could be easy integrated with other systems. The experimental results show that the proposed algorithm and architecture has better performance than previous work. Comparing the traditional analog TV display, larger size/higher resolution and progressive scan is the trend. Translating the interlaced video to the progressive format is still an open research problem. In the third part, a motion adaptive de-interlacing algorithm is presented. It consists of the ELA-median directional interpolation, same-parity 4-field horizontal motion detection, morphological operation for noise reduction and adaptive threshold adjusting. The edges can be sharper when the ELA-median directional interpolation is adopted. The same-parity 4-field horizontal motion detection detects faster motion and makes more accurate determinations about where objects are going to move. The morphological operation for noise reduction and adaptive threshold adjusting preserve the actual texture of the original objects. The proposed method achieves cost-efficient hardware implementation with low complexity, low memory usage, and high-speed processing capability. The experimental results show that the proposed algorithm is more cost-effective than previous systems. In several wireless hand-held systems, the finite impulse response (FIR) filters are the indispensable parts among various image/video communication applications to reduce noise and to enhance the specific features. With a given specification, the dedicated filter is designed to fit in the applications and has the least effect of redundancy. At last part, a novel approach for implementing power-efficient finite impulse response (FIR) filters is proposed. The proposed schemes can be adopted in the direct form FIR filter and achieve a large amount of reduction in the power consumption. By using a combination of proposed methods, balanced-modular techniques with retiming and separated processing data flow scheme with modified CSD representation. Experimental results show that the proposed scheme reduce 76% power consumption of the original direct-form structure with slight area overhead. These techniques can greatly improve the video quality and be suitable implemented for real-time digital TV systems.

並列關鍵字

Filter Chip Deinterlace VLSI

參考文獻


[3] H.-M. Hang and J. Woods, Handbook of Visual Communications, Academic Press, 1995.
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[8] ITU-T Recommendation H.261: “Video Codec for Audiovisual Services at p
[1] Katsuya Hasegawa, Kazutake Ohara, Akihisa Oka, Takehiro Kamada, Yasuhiro Nagaoka, Katsuhisa Yano, Eiji Yamauchi, Takao Kashiro, Tomoo Nakagawa “Low-Power Video Encoder/Decoder Chip Set For Digital VCRs” IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, pp. 1780 -1788, Nov. 1996.

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