應用於晶片間傳輸之時脈誤差校正電路設計

莊璦嘉

doi:10.6845/NCHU.2012.00136

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應用於晶片間傳輸之時脈誤差校正電路設計

Design of a Clock-Deskew Buffer Circuit for Chip-to-Chip Links

莊璦嘉 , Masters　　Advisor：楊清淵　　

繁體中文 DOI： 10.6845/NCHU.2012.00136

時脈誤差校正緩衝器；雙向傳輸緩衝器；延遲鎖定迴路；低電壓差動訊號傳輸器； clock-deskew buffer ； bidirectional buffer ； delay-locked loop ； low-voltage differential signaling (LVDS) transmitter

Abstract │ Reference (41) │ Altmetrics

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With the rapid advances in CMOS technology, the demand for highly integrated VLSI circuit has grown exponentially in recent years. As the system frequency is rising, the problem of timing jitter for circuit modules is more serious. It will decrease the speed and the responsibility, if the timing jitter is too high. So in modern high-speed systems, the skew-free distribution of clocks is very critical for synchronous circuits and the clock-skew problem will become a significant subject.

In this thesis, several architectures which may be used to correct clock skew are introduced. A novel clock-deskew buffer with a latch-based dual delay-locked loop (LBD-DLL) technique is proposed to synchronize the clocks for a chip-to-chip system without delay measurements and dummy delay elements. The LBD-DLL can operate in high frequencies by using the low-voltage differential architecture for the interfaced I/Os. Fabricated in TSMC 0.18-um CMOS process, the circuit can provide the output frequency range of 750MHz to 1.5GHz and the chip area is 0.964mm×0.975mm. When the operation frequency is 1.5GHz, the peak-to-peak jitter of the output clock is 8.89ps and total power dissipation is 33mW under a 1.8-V supply voltage.

Furthermore, in order to provide wide operation range, a wide-range clock-deskew buffer is proposed in the second word. The wide-range operation is achieved in multi-band voltage controlled delay line. This chip is also fabricated in TSMC 0.18-um CMOS process. From the simulation results, we can demonstrate that this clock-deskew buffer can operate from 20MHz to 2GHz. When the operation frequency is 2GHz, the peak-to-peak jitter of the output clock is 9.81ps and total power dissipation is 40mW under a 1.8-V supply voltage. The chip area is 1.39mm×1.39mm.

Reference ( 41 ) 〈TOP〉

[5]C. Y. Yang and S. I. Liu, “A one-wire approach for skew-compensating clock distribution based on bidirectional techniques,”IEEE Journal of Solid-State Circuits, vol. 36, pp. 266-272, Feb. 2001.
連結：
[7]A. Coban, M. H. Koroglu, and K. A. Ahmed, “A 2.5-3.125Gb/s quad transceiver with second order analog DLL-based CDR’s,” IEEE Journal of Solid-State Circuits, vol. 40, pp. 1940-1947, Sep. 2005.
連結：
[8]G. Chien and P. R. Gray, “A 900MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 1995-1996, Dec. 2000.
連結：
[9]G. K. Dehng, J. M. Hsu, C. Y. Yang and S. I. Liu, “Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop,” IEEE Journal of Solid-State Circuits, vol. 35, No. 8, pp. 1128-1136, Aug. 2000.
連結：
[12]S. K. Kao and S. I. Liu, “ A Delay-Locked Loop With Statistical Background Calibration,” IEEE Transactions on Circuits and Systems-II：Express Briefs, vol. 55, pp. 961-965, Oct. 2008.
連結：

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