應用於VP8以及H.264/AVC視訊標準區塊消除濾波器之硬體共享架構設計與實現

周育霖

doi:10.6845/NCHU.2012.01037

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應用於VP8以及H.264/AVC視訊標準區塊消除濾波器之硬體共享架構設計與實現

A Hardware Sharing Architecture of Deblocking Filter for VP8 and H.264/AVC Video Coding

周育霖 , Masters　　Advisor：吳崇賓　　

英文 DOI： 10.6845/NCHU.2012.01037

區塊消除濾波器；硬體共享架構； H.264/AVC ； VP8 ； Deblocking Filter ； Hardware Sharing Architecture

Abstract │ Reference (30) │ Altmetrics

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In this thesis, a hardware sharing architecture to perform the multi-standard deblocking filter that support VP8 and H.264/AVC is proposed. First, a reorganization of deblocking filter is used to derive a common architecture which is suitable for H.264/AVC and VP8. The proposed design is then reused for the whole filtering. To further reduce the computational complexity, highly sharing architecture is also presented. In order to save the size of the on-chip memory, a memory sharing architecture of the deblocking filter and motion compensation is introduced. We also reorganize the processing order of filtering to reduce the total on-chip memory size. 
According to the experimental results, the adopted hardware sharing architecture saves 63.3% of shifters, 77.4% of adders and 100% of multipliers totally. The overall PSNR drops less than 1% on the VP8 decoder for low complexity applications. Finally, a hardware implementation using TSMC 0.18 μm cell library is performed. The clock frequency of the proposed hardware is working at 130 MHz to perform deblocking filter for supporting Full HD 1080P@30fps. The implementation results show that the gate count of this architecture adopted on VP8 and H.264/AVC video codec system is 43.2K.

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[3] T. Wiegand, G. J. Sullivan, G. Bjontegaard, and A. Luthra, “Overview of the H.264/AVC video coding standard,” IEEE Trans. Circuits Syst. Video Technol., vol.13, no.7, pp.560-576, July 2003.
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[4] S. Srinivasan, “Windows Media Video 9: Overview and applications,” Signal Process.: Image Commun., vol. 19, pp. 851-875, 2004.
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[6] J. Bankoski, P. Wilkins, and Y. Xu, “Technical overview of VP8, an open source video codec for the web,” in Proc. IEEE Int. Conf. Multimedia and Expo (ICME), July 2011, pp.1-6.
連結：
[8] V. Lappalainen, A. Hallapuro, T. Hamalainen, “Complexity of optimized H.26L video decoder implementation,” IEEE Trans. Circuits Syst. Video Technol., vol.13, no.7, pp. 717- 725, July 2003.
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[11] M. Parlak, and I. Hamzaoglu, “Low power H.264 deblocking filter hardware implementations,” IEEE Trans. Consum. Electron., vol.54, no.2, pp.808-816, May 2008.
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