蝕刻參數對矽淺溝槽圖形影響與研究

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蝕刻參數對矽淺溝槽圖形影響與研究

The Influence of Etch Parameters on Silicon Shallow Trench profile

唐維翎 , Masters　　Advisor：顏秀崗　　

繁體中文

半導體；蝕刻； Semiconductor ； Etch ； Trench

Abstract │ Reference (31) │ Altmetrics

Abstract 〈TOP〉

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Due to the demand of large data processing, the low power consumption, high process speed and high capacitor of memory are increasing drastically. For this purpose, it is necessary to shrink the chip size of dynamic random access memory (DRAM) and improve the related functions. However, by physical limits, it is more difficult to scale down the transistors. For the new generation of high density 4F2 transistor, “Vertical Pillar Transistor (VPT)” with well control ability on “Gate”, VPT is one of the best choices for 4F2 array transistor.
	For scaling down and low package bulk, VPT is a device that burying “Bit Line” and “Word Line” into silicon. For burying word/bit line process, etching bit line trench and then word line trench was carried out to get transistor channel (silicon pillar) in this study. Base on 40 nm process, a vertical profile of silicon trench may be achieved by adjusting etching parameters.
	There are three different process were tried. (1) Due to its good critical dimension (CD) control ability, hydrogen bromide (HBr) was used as the primary etching gas. In this experiment, argon (Ar) is added in for ion bombard improvement. Although good CD control and flat bottom of silicon were derived, a bowing profile was observed. (2) SF6/CF4/CHF3 mixed gas was used for the primary etching and O2/N2 for CD/trench profile control, i.e. controlling the amount of polymer produced during etching process. As a result, a large amount of F- (high electro-negativity) dissociated from SF6, a serious side wall etching profile of silicon trench was observed, i.e. a worse CD control. (3) Cl2/CF4/CHF3 mixture was used as the major etching gas in the first etch step and NF3/Cl2/CF4/CHF3 mixture as the major etching gas in the second etch step. Then a vertical silicon trench profile is derived, leading to a possible process in manufacturing high density 4F2 array transistor.

Reference ( 31 ) 〈TOP〉

[1] Jae-Man Yoon, Kangyoon Lee, Seung-Bae Park, Seong-Goo Kim, “A Novel Low Leakage Current VPT(Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40 nm Technology”, IEEE , 1548-3770,p259 - 260,2006.
連結：
[2] Hyejin Shin, Kiho Yang, Jinyoung Choi, Jinsoo Kim, “The Analysis of Optical Lithography at 2-Dimensional Dense Structure ”, Proc. of SPIE Vol. 6924, 69244V, 2008.
連結：
[3] Dr. Kinam Kim , SAIT1, Samsung Electronics Co. , Yongin-City, Gyunggi-Do, Rep. of Korea , “From The Future Si Technology Perspective: Challenges and Opportunities” , IEEE , 0163-1918 , p1.1.1 - 1.1.9 , 2010.
連結：
[6] D.H. Kim et al., IEDM Tech. Dig., pp. 69-72, 2004.
連結：
[9] Hyunwoo Chung, Huijung Kim, Hyungi Kim, Kanguk Kim , “Novel 4F2 DRAM Cell with Vertical Pillar Transistor(VPT)” , IEEE , 1930-8876 , p 211 - 214 , 2011.
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