填充矽通孔之新穎電鍍銅配方

陳偉翔

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填充矽通孔之新穎電鍍銅配方

A Novel Copper Electroplating Formula for Filling Through Silicon Vias

陳偉翔 , Masters　　Advisor：竇維平　　

繁體中文

電鍍；矽通孔；銅導線；沉積銅；三維晶片堆疊； eletroplating ； through silicon vias ； copper deposition ； 3D chip stacking ； interconection

Abstract │ Reference (64) │ Altmetrics

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The development of modern science and technology proceeds quicker and quicker. Three-dimensional (3D) integration of chips is fast growing to carry out high-speed performance and high-density packaging. 3D integration uses through-silicon-vias (TSVs) to interconnect multiple active circuit layer in a single chip, that performs high density interconnects with a small form factor. This thesis achieves void-free TSV filling using electrochemical deposition (ECD) of copper, because a void formed in the TSV may cause serious reliability issues. 
Since the aspect ratio of the TSV is much higher than that of the vias of printed circuit boards (PCBs), a common copper plating formula for PCBs cannot fully fill the TSV with copper deposit. In this thesis, some novel organic additives were screened by chronopotentiometry to be levelers. Electroanalytical measurements and feature-filling experiments were carried out to study the effect of these additives.
Copper electroplating formulas with multi-component and with single component for TSV filling were developed. TTC is a new additive, which is appropriate for TSV filling in multi-component method. A trapezium-type profile of the top copper deposit in the filled TSV was achievable using the plating formula with TTC. This plating process can make sure of no void and seam formation during plating. TV was a novel additive for filling TSV in a single component system. Surprisingly, the thickness of copper on the wafer surface was a constant during the plating process, indicating that the copper deposition is highly selective. The high selectivity of copper fill greatly reduces the loading of chemical mechanical polishing (CMP) and saves the process time of TSV.
The insulating layer, barrier layer and copper seed layer were formed inside the TSV before copper electrodeposition. However, the step coverage of sputtered copper seed layer was not good enough. A void-free filling of the TSV is not only achieved by an excellent plating formula but also by good continuity and conformality of the seed layer. The thickness of the seed layer coated on the via wall has significant effect on the TSV filling. If the seed layer is not continuous, then a void-free filling of the TSV is not achievable. In this work, we developed another plating formula to repair the discontinuous seed layer rendering it to be continuous and conformal. Thus, the TSV with a high aspect ratio were fully filled after repairing the seed layer using the special plating formula.

Reference ( 64 ) 〈TOP〉

1.Prentice-Hall, “Introduction of semiconductor Manufacturing Technology”, p.447, New Jersey, 2001.
連結：
4.K. Kondo, T. Nakamura, D. Mikami, T. Ookubo “Via Filling Electrodeposition by Using Periodical-Reverse Pulse Current”, Journal of The Electrochemical Society., 6, 135, 2007.
連結：
5.J. J. Sun, K. Kondo, T, Okamura, S. Oh, M. Tomisaka, H, Yonemura, M. Hoshion, and K. Takahashi, “High-Aspect-Ratio Copper Via Filling Used for Three-Dimensional Chip Stacking,” Journal of The Electrochemical Society., 150, 355, 2003.
連結：
6.K. Kondo, T. Yonezawa, D. Mikami, T. Okubo, Y. Taguchi, K. Takahashi, and D. P. Barkey,“High-Aspect-Ratio Copper-Via-Filling for Three-Dimensional Chip Stacking”, Journal of The Electrochemical Society., 152, H173, 2000.
連結：
7.L. Xu, P. Dixit, J. miaro, J. H. L. Pang, X. Zhang, K. H. Tu, and R. Preisser “Through-wafer electroplated copper interconnect with ultrafine grains and high density of nanotwins”, Applied Physics Letters., 90, 03311, 2007.
連結：

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