stands for Digital Object Identifier
and is the unique identifier for objects on the internet. It can be used to create persistent link and to cite articles.
Using DOI as a persistent link
To create a persistent link, add「http://dx.doi.org/」
before a DOI.
For instance, if the DOI of an article is 10.5297/ser.1201.002 , you can link persistently to the article by entering the following link in your browser: http://dx.doi.org/ 10.5297/ser.1201.002 。
The DOI link will always direct you to the most updated article page no matter how the publisher changes the document's position, avoiding errors when engaging in important research.
Cite a document with DOI
When citing references, you should also cite the DOI if the article has one. If your citation guideline does not include DOIs, you may cite the DOI link.
DOIs allow accurate citations, improve academic contents connections, and allow users to gain better experience across different platforms. Currently, there are more than 70 million DOIs registered for academic contents. If you want to understand more about DOI, please visit airiti DOI Registration （ doi.airiti.com ） 。
石逸群 , Masters Advisor：武東星
P 通道金屬氧化物半導體電容元件 ； N通道金屬氧化物半導體電容元件 ； 去耦合電漿氮化 ； 閘極保護層 ； 硼穿透 ； 閘極空乏 ； P-type channel metal-oxide-semiconductor capacitor (PMOS) ； N-type channel metal-oxide-semiconductor capacitor (NMOS) ； Decoupled plasma nitridation (DPN) ； Gate barrier oxide ； Boron penetration ； Poly depletion
-  K. M. Cham, D. W. Wenocur, J. Lin, C. K. Lau, H. –S. Fu, “ Submicrometer Thin Gate Oxide P-Channel Transistors with P+ Polysilicon Gates for VLSI Applications,” IEEE ELECTRON DEVICE LETTERS, vol. EDL-7, no. 1, pp. 49 – 52 Jan. 1986.
-  M. J. Deen, and Z. X. Yan, “ Substrate Bias Effects on Drain-Induced Barrier Lowering in Short-Channel PMOS Devices,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 37 no. 7, pp. 1707 – 1713 Jul. 1990.
-  R. R. Troutman, “ VLSI Limitations from Drain-Induced Barrier Lowering,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. ED-26, no. 4, pp. 461 – 469 Apr. 1979.
-  A. H. Montree, V. M. H. Meijssen and P. H. Woerlee, “ Comparison of buried and surface channel PMOS devices for low voltage 0.5 um CMOS,” in Proc. VLSI Technology, Systems, and Applications, (VTSA’93), 1993, pp. 11 – 14.
-  N. Lifshitz, “ Dependence of the Work-Function Difference Between the Polysilicon Gate and Silicon Substrate on the Doping Level in Polysilicon,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. ED-32, no. 3, pp. 617 – 621 Mar. 1985.
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