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  • 學位論文

以功率轉換研究45 nm MOSFETs 高溫熱載子效應的直流與交流壽命

Using Power Transform to Study the DC and AC Lifetimes of High Temperature Hot-Carrier Effect on MOSFETs of 45 nm Node and Beyond

指導教授 : 陳雙源 黃恆盛
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摘要


新世代的金氧半場效電晶體(MOSFET)已普遍使用二氧化鉿(HfO2)來當閘極介電層,但其熱載子可靠度問題,仍是值得研究的課題,本研究團隊曾利用功率轉換研究65 nm MOSFETs的熱載子可靠度問題,得到另人滿意的結果,本研究則持續研究功率轉換應用於45 nm nMOSFETs的效果。 本實驗中我們使用聯華電子所提供的測試元件45 nm製程的nMOSFETs元件。測試條件為通道長度/寬度(W/L)=10/0.1um以及通道長度/寬度(W/L)=10/0.05um的元件,並在25℃、55℃、85℃溫度進行實驗,應力測試電壓(VG;VD)分別設為(2.7 ; 2.7)、(2.7 ; 2.9)、(2.7 ; 3.1)、(2.9 ; 2.7)、(2.9 ; 2.9)、(2.9 ; 3.1)、(3.1 ; 2.7)、(3.1 ; 2.9)、(3.1 ; 3.1), 進行直流(DC)、交流(AC)通道熱載子(CHC)實驗。 把做出來的實驗結果套用於功率轉換模式之中,發現功率轉換模式可以成功地描述元件劣化的情況,並可發現在較高應力電壓以及溫度下,元件所造成的劣化較為嚴重,此結果可用於產業界用來預測劣化的情況,並且能夠減少測試元件的時間,提高工作的效能。

關鍵字

熱載子 轉換功率 直流 交流

並列摘要


MOSFETs use HfO2 as the gate dielectrics in the new generation, but they still have hot-carrier problem, and more studies are need. Our team invented the Power Transform Model to study hot-carrier reliability of 65 nm MOSFETs in the past, and the results of the study were good. Hence, Power Transform Model applied in 45 nm nMOSFETs is studied in this work. In this research, the tested devices were 45 nm nMOSFETs from United Micro-electronics Corporation (UMC). The device channel width/length (W/L) = 10/0.1um and (W/L) = 10/0.05um. All tests were conducted at temperatures 55℃. and the stress voltage of VD and VG were (2.7 ; 2.7)、(2.7 ; 2.9)、(2.7 ; 3.1)、(2.9 ; 2.7)、(2.9 ; 2.9)、(2.9 ; 3.1)、(3.1 ; 2.7)、(3.1 ; 2.9)、(3.1 ; 3.1), respectively. Stress modes were DC and AC on channel hot-carrier (CHC) conditions. From the CHC test results, it is found that the power transform model can successfully describe device damage.

並列關鍵字

Hot-carrier transformed power DC AC

參考文獻


[2.11] C. Hu, S. C. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan and K. W. Terrill, “Hot-electron-induced MOSFET degradation-model, monitor, and improvement,” IEEE Journal of Solid-State Circuits, vol. sc-20, no. 1, 1985, pp. 295-305.
[1.1]. M. Song, K. P. MacWilliams, J. C. S Woo, “Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K,” IEEE Transactions on Electron Devices, vol. 44, no. 2, February, 1997, pp. 268-276.
[2.1] S. E. Kerns, “Characterization and modeling of hot-carrier degradation in sub-micron nMOSFETs,” August. 2002.
[2.2] C. T. Wang, “Hot carrier design considerations for MOS devices and circuits,” July, 1992.
[2.4] M. Song, K. P. MacWilliams, J. C. S Woo,, “Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K,” IEEE Transactions on Electron Devices, vol. 44, no. 2, February, 1997, pp. 268-276.

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