透過您的圖書館登入
IP:3.137.178.133
  • 學位論文

以轉換功率之壽命模型預測交直流測試下的高溫熱載子劣化情形

A Lifetime Model with Transformed Power for Predicting the High Temperature Hot-Carrier Degradation under DC and AC Stress

指導教授 : 黃恆盛 陳雙源

摘要


長久以來,熱載子(hot-carrier, HC)效應一直是研究MOSFET元件劣化的重要議題,過去文獻多在描述直流(DC)測試下的熱載子壽命模型。然而,無論這些模型有多精準,也無法確切表達元件實際應用在交流(AC)電路下的劣化情形。因此本實驗以轉換功率(transformed power)的方式,研究並預測在交直流加壓測試下元件壽命之劣化情形。 實驗使用聯華電子公司(UMC)提供的65奈米製程晶圓,所研究的MOSFET元件通道長寬比為1 μm / 0.05 μm (N型)及1 μm / 0.06 μm (P型)。介電層為SiON,厚度19.5 Å。在25 ℃、85 ℃和125 ℃三種不同溫度下,進行DC與AC的通道熱載子實驗。此外同時考慮電壓、電流以及溫度的影響,提出修正後的功率轉換法,用以找出有關熱載子可靠度的交直流壽命。 由實驗結果顯示,不論N型或P型的MOSFET元件,以功率轉換的方式皆可成功描述元件劣化情形,因此可使用此模型做交直流測試下的壽命預測。其中,在低頻與高頻的交流測試下,隨著閘極提供的信號週期越長,雖然總轉換功率(Ptotal)不因頻率不同而有太大變化,但元件仍然呈現較為劣化的狀況。另一方面,由功率轉換模型的參數變化可得知,溫度升高源極功率(Psource)會降低而基極功率(Pbulk)會提升。而元件壽命的預測結果顯示,在高測試電壓下功率轉換模型較傳統模型樂觀,且在操作電壓下使用傳統模型預測可能會高估元件劣化情形。 本研究重要性在於,建立一個創新的壽命模型,且證明元件劣化至失效可視為總轉換功率的能量所導致。希望此研究成果可使晶圓廠或積體電路設計者接受從功率的觀點看待元件劣化情形,並能用於預測元件的交直流壽命。

關鍵字

熱載子 直流 交流 轉換功率 壽命模型

並列摘要


Hot-carrier (HC) effect has been an important issue to investigate degradation of MOSFETs for a long time, and the associated HC lifetime models presented in the past were mostly derived from DC stress. However, no matter how accurate these models are, they can not be precisely suitable for the damage of in-circuit MOSFET properties applying on AC operation practically. For this reason, this research continues to develop the transformed power method to study and predict MOSFET lifetime on either DC or AC stress. In this work, the wafers were supplied from 65 nm technology of United Micro-electronics Corporation (UMC) and were made for reliability study. The tested n-type MOSFETs have channel length/width equal to 1/0.05 (μm/μm), and 1/0.06 (μm/μm) for p-type. The thickness of SiON gate dielectric is 19.5 Å. Furthermore, stress modes are set on DC and AC channel hot-carrier (CHC) conditions at three different temperatures, 25 ℃, 85 ℃, and 125 ℃. In addition, a modified way of power transform method, which consists of voltage, current, and temperature, is proposed to find the DC and AC lifetimes of MOSFETs based on CHC reliability consideration. From the CHC test results of either nMOSFETs or pMOSFETs, it is found that the power transform model can successfully describe device damage and thus the model can be use for lifetime prediction in DC and AC stress. And, under the AC stress, the device degradation is much worse as the period applied in the gate terminal becoming longer. This case is valid for high and low frequency, although the total transformed power (Ptotal) has little change with different frequencies. On the other hand, the variance in parameter of power transform model reveals that the elevated temperature is able to cause the source power (Psource) become lower, and it also reflects the increment on the bulk power (Pbulk) simultaneously. The result of predicting device lifetime shows that the power transform model is more optimistic than the conventional model under high stress voltage, and using the conventional model, at operation region, could overestimate the degradation of the MOSFETs. Consequently, the significance of this work is to establish an innovative lifetime model to demonstrate that the total transformed power may be regarded as the quantity to cause device failure. And this model can be used to accurately forecast the lifetime of in-circuit devices in either DC or AC operations. It is hope that this research will enable the wafer foundries and IC design houses to conceive the MOSFET degradation from the point of view of total power applied on it.

並列關鍵字

Hot-carrier DC AC transformed power lifetime model

參考文獻


[1.1] P. Chaparala and D. Brisbin, “Impact of NBTI and HCI on PMOSFET threshold voltage drift,” Microelectronics Reliability, vol. 45, 2005, pp. 13-18.
[1.2] S. Y. Chen, C. H. Tu, J. C. Lin, P. W. Kao, W. C. Lin, Z. W. Jhou, S. Chou, J. Ko, and H. S. Haung, “Temperature effect on the hot-carrier induced degradation of pMOSFETs,” IIRW Final Report, 2006, pp. 163-166.
[1.3]. M. Song, K. P. MacWilliams, J. C. S Woo, “Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K,” IEEE Transactions on Electron Devices, vol. 44, no. 2, February, 1997, pp. 268-276.
[1.4] E. Takeda, Y. Nakagome, H. Kume, S. Asai, “New hot-carrier injection and device degradation in submicron MOSFETs,” IEEPROC, vol. 130, no. 3, June. 1983, pp. 144-150.
[1.5] C. Hu, S. C. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan and K. W. Terrill, “Hot-electron-induced MOSFET degradation-model, monitor, and improvement,” IEEE Journal of Solid-State Circuits, vol. sc-20, no. 1, 1985, pp. 295-305.

延伸閱讀