具不同Si-Cap厚度的SiGe源/汲極應變PMOSFETs之特性分析

林聖融

doi:10.6841/NTUT.2010.00293

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具不同Si-Cap厚度的SiGe源/汲極應變PMOSFETs之特性分析

Characteristics of SiGe Source/Drain Strained PMOSFETs with Different Si-Cap Thickness

林聖融 , Masters　　Advisor：黃恆盛;陳雙源　　

英文 DOI： 10.6841/NTUT.2010.00293

應變矽；矽鍺源/汲極；雙軸應變； Strained-Si ； SiGe Source/Drain ； bi-axial strain

Abstract │ Reference (37) │ Altmetrics

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SiGe source/drain strained-Si technology involves etching out the source/drain area of a pMOSFET and replacing it with SiGe. The device performance can be improved due to the lattice mismatch between silicon and germanium which makes the silicon in channel generating compressive strain.
    Previous literatures have revealed the effect of MOSFETs with different gate length with uni-axial SiGe-S/D strain. But the studies of pMOSFETs having bi-axial strain using very thin Si-cap thickness and SiGe-S/D simultaneously haven’t been much investigated yet. In this work, we examine and analyze the characteristics of devices containing bi-axial and uni-axial SiGe-S/D strain in various gate lengths with different thin Si-cap thickness (9, 24, 39 &Aring;). Besides, discussion and explanation of the difficulty in applying traditional silicon device models and theorems (BSIM model, channel-resistance method etc.) because of using strain technique are also provided in this thesis.
The experimental results show that in long channel, with Si-cap thickness becomes thinner, the device performance enhances more. This is thanks to both the hole-population distribution across the Si-cap/SiGe-channel layers during inversion and hole mobility enhancement in the global strain channel. In short channel, Si-cap encounters seriously compressive stress and generates certain amount of defects. Especially when Si-cap= 9 &Aring;, performance of the pMOSFETs reduces instead. The gate leakage current increases while Si-cap thickness decreasing. Therefore, this study suggests that Si-cap thickness is required to be more than 24 &Aring; at least.
    This research also investigates the carrier mobility in linear and saturation region. Most research used to extract the carrier mobility by trans-conductance method. However, most MOSFETs actually operate in saturation region with high electric field.  Therefore, it is important to extract carrier mobility from saturation region. By comparing with Si control devices, the mobility enhancement of strain pMOSFETs extracting by Idsat method is approximately an half to that by gm maximum method. This result shows that there are factors, such as velocity saturation, limiting the mobility enhancement in saturation region.

Reference ( 37 ) 〈TOP〉

[1-2] C. K. Maiti, “Strained-Si Heterostructure Field Effect Devices: Strain-Engineering in CMOS Technology,” Physics of Semiconductor Devices, 2007. IWPSD 2007.
連結：
[2-1] S. H. Olsen, A. G. O’Neill, S. Chattopadhyay, L. S. Driscoll, et al., “Study of Single- and Dual-Channel Designs for High-Performance Strained-Si-SiGe n-MOSFETs,” IEEE Transactions on Electron Devices, Vol. 51, No. 7, July 2004.
連結：
[2-2] J. L. Liu, C. D. Moore, G. D. Uren, Y. H. Luo, et al., “A surfactant-mediated relaxed Si0.5Ge0.5 graded layer with a very low threading dislocation density and smooth surface,” Applied Physics Letters, Vol. 75, P. 1586, 1999.
連結：
[2-3] Y. H. Luo, J. Wan, R. L. Forrest, J. L. Liu, et al., “Compliant Effect of Low-Temperature Si Buffer for SiGe Growth,” Applied Physics Letters, Vol. 78, P. 454, 2001.
連結：
[2-4] Z. Y. Cheng, M. T. Currie, C. W. Leitz, G. Taraschi, et al., “Electron Mobility Enhanvement in Strained-Si n-MOSFETs Fabricated on SiGe-on-Insulator (SGOI) Substrates,” IEEE Electron Letters, Vol. 22, P. 321. 2001.
連結：

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