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  • 學位論文

熱載子與負偏壓溫度不穩定性導致深次微米及奈米pMOSFET劣化之研究

Investigations of Hot-Carrier and Negative Bias Temperature Instability Induced Degradation on Deep Submicron and Nanometer pMOSFETs

指導教授 : 黃恆盛 陳雙源

摘要


有關熱載子(hot carrier, HC)造成p通道金氧半場效應電晶體(p-channel metal-oxide-semiconductor field-effect transistors, pMOSFETs)劣化的問題,雖已有不少研究,但隨元件尺寸的縮小,提升了電路中元件的密集度,使得元件在高溫操作的機會大為增加,加上近年pMOSFETs之負偏壓溫度不穩定性(negative bias temperature instability, NBTI)成為重要可靠度問題之ㄧ,因此,考慮溫度效應,了解HC與NBTI對不同世代之pMOSFETs的最劣化情況是重要的。其次,本論文亦以退火實驗研究其恢復效應,進一步了解NBTI造成特性恢復的機制。論文最後則探討上述可靠度問題引起電路中元件特性失匹配的問題。 本論文首先以0.13 μm, 90 nm, 及 65 nm世代的pMOSFETs作HC與NBTI應力測試,探討最劣化應力條件的問題。經不同溫度與應力電壓的實驗證明,三種世代下,最劣化情況皆是發生在高溫下的通道熱載子(channel HC, CHC)模式,進一步得知高溫之CHC的劣化較NBTI嚴重,推測元件特性因CHC應力所產生的劣化是由於熱載子與NBTI兩者共同造成,論文最後利用壽命模型預測其元件壽命。 另一方面,文獻上對於NBTI恢復現象的原因尚未有更完善的解釋,為了解其機制,本論文利用含氮氣(nitrogen molecule, N2)與氫氣(hydrogen molecule, H2)的高溫退火研究NBTI恢復效應,結果發現大量的Nit可再被鈍化形成Si-H鍵結,使元件特性恢復。同時,由結果推論H可能無大量地擴散至介電質層內,應是多停留於介電質層與矽基體的介面(the gate dielectric/Si-bulk interface)附近。根據反應-擴散模型(reaction-diffusion model, R-D model)的觀點,推測NBTI導致特性的劣化及恢復與R-D model中的反應(reaction)模式較有關,與擴散(diffusion)模式較無關。 論文最後一個主題是探討CHC與NBTI導致pMOSFETs特性失匹配(mismatch)的問題,經實驗證明上述兩種可靠度應力導致元件劣化的同時,也會使電晶體對(transistor pairs)的失匹配問題更嚴重,對於小尺寸的元件會更明顯。同時隨著應力時間的增加,CHC導致pMOSFETs特性失匹配的程度有比NBTI更嚴重的趨勢,其可能原因應是由於熱載子與NBTI兩效應共同貢獻所致,進一步推論其機制應是與隨機陷阱(random traps)的產生有關。

並列摘要


It is well-known that hot-carrier (HC) effect is a key reliability problem for wafer foundries and design houses. As the metal-oxide-semiconductor field-effect transistors (MOSFETs) continue shrinking into deep submicron and nanometer regimes to increase the circuit density, the MOSFETs are unavoidably operated at high temperature. Then, temperature effect needs to be considered in the MOSFET reliability tests. In recent years, p-channel MOSFET (pMOSFET) degradation induced by NBTI (negative bias temperature instability) catches much attention as the device size is shrinking. Besides, NBTI effect has two phenomena include the degradation phase and the recovery phase. Therefore, it is so important to understand the severity of the above-mentioned reliabil-ity issues on pMOSFETs in current and future technologies. On the other hand, in this dissertation, NBTI recovery effect is investigated by using different annealing treatment to understand the recovery mechanism. Also, pMOSFET mismatch induced due to reli-ability stress is critical for wafer manufactures and circuit applications. The HC and NBTI stress-induced pMOSFET mismatches are investigated. The problem focused on this work is the most critical stress mode that should be employed in the HC and NBTI reliability tests. Through many experiments, on pMOS-FETs of 0.13 μm, 90 nm, and 65 nm generations, all results clearly show that the most critical stress mode occurs in channel HC (CHC) stress mode. And, CHC at high tem-perature is worse than NBTI. It is supposed that CHC-induced pMOSFET degradation is involved with the contribution of HC and NBTI effects. In addition, the lifetimes of pMOSFETs are predicted for the different stress modes. On the other hand, in this dissertation, NBTI recovery effect with N2 (nitrogen molecule) and H2 (hydrogen molecule) annealing treatment is also investigated. The re-sults show that the pMOSFET characteristics are recovered after annealing. The results prove that ΔNit can be recovered apparently and dominates the improvement of pMOS-FET characteristics. ΔNot recovery is also observed but only possesses a small portion in our experiments. Thus, the recovery of large ΔNit after anneal is conjectured to be due to most of the released H species staying near the interface of SiO2/Si-bulk. Therefore, it is suggested that only reaction mode takes place during the degradation and the recovery, minor or no diffusion mode has occurred. The last subject of this dissertation is the pMOSFET mismatches induced by CHC and NBTI stresses. This work reported that, as aging time is increasing, CHC-induced pMOSFET mismatches are gradually worse than those of NBTI. The cause is presum-able for the integration of HC and NBTI effects. The mechanism is inferred to be the creation of random traps in the SiON gate dielectric and at the SiON/Si-bulk interface.

參考文獻


[1.1] Taiwan Semiconductor Industry Association (TSIA), Taiwan, http://www.tsia.org.tw/
[1.8] C. Hu, S. C. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan, and K. W. Terrill, “Hot-electron-induced MOSFET degradation-model, monitor, and improve-ment,” IEEE Journal of Solid-State Circuits, vol. SC-20, no. 1, 1985, pp. 295-305.
[2.7] C. Hu, S. C. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan, and K. W. Terrill, “Hot-electron-induced MOSFET degradation-model, monitor, and improve-ment,” IEEE Journal of Solid-State Circuits, vol. SC-20, no. 1, 1985, pp. 295-305.
[1.3] Intel Corporation, USA,
[1.4] K. Xiu and M. Ketchen, “Thermal modeling of a small extreme power density macro on a high power density microprocessor chip in the presence of realistic packaging and interconnect structure,” Electronic Components and Technology Conf., 2004, pp. 918-923.

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