低成本可重新架構色彩內插影像處理器積體電路架構設計

VLSI architecture of a cost-efficient reconfigurable colour interpolation image processor design

趙文瑄(Wen-Xuan Zhao)

指導教授 ： 陳世綸

中原大學/電機資訊學院/電子工程研究所/碩士(2017年)

https://doi.org/10.6840/cycu201700771

摘要

本論文提出低成本的色彩補償演算法，可實現於即時性色彩內插影像處理積體電路設計，在演算法部分以低成本、高品質為設計基礎，演算法中包含的濾波器技術，分別為空間銳化濾波器與拉普拉斯濾波器的技術，可減少邊緣像素點資訊的不足，增強模糊的細節，提高影像還原品質，在設計上以低複雜度為基礎，係數方面以2的倍數來運算，如此一來，在硬體部分，可使用位移器取代乘法器，大幅地降低電路成本，並搭配兩條線緩衝記憶體，讓影像處理器電路可以順利處理像素點資訊，而不遺失所需運算之像素點資訊。本論文將參考文獻[1]的主要運算電路，使用電路硬體共用技術，此項技術可以大大地降低硬體成本，提升邏輯使用率，並共用加法、減法與位移器提升邏輯使用率，共用加法、減法、位移器。
電路設計完成後，先以FPGA驗證電路功能是否正確，先以FPGA驗證電路功能正確以後，再經過Design Compiler合成電路經過Design Compiler合成電路，最後使用IC Compiler光罩佈局繞線進行晶片實現再使用IC Compiler光罩佈局繞線，實現晶片。本論文之演算法，沿用先前參考文獻[1]，在影像評估公式維持影像品質，而在硬體部份，工作頻率可到達200MHz，邏輯閘數目為2.58K，在台積電0.18μm的CMOS製程下在0.18um的CMOS製程下，佈局面積為32.2k μum2，相較於先前參考文獻，本論文有效地降低11%之邏輯閘數目。

關鍵字

色彩濾波陣列 ； 色彩補償 ； 色彩內插 ； 去馬賽克 ； 空間銳化濾波 ； 拉普拉斯濾波

並列摘要

This thesis presents a low-complexity algorithm for interpolating colour compensation. The proposed colour interpolation algorithm was implemented by a low-complexity and real-time image processing integrated circuit design.
The proposed design is based on a low-cost and high-quality algorithm. It consists of two filters which are Laplacian filter and spatial sharpening filter. The Laplacian filter and spatial sharpening filter reduce the lack of boundary information and enhance the details of the fuzzy regions to increase the interpolated image quality. All multiple operations in the procedure of the proposed low-complexity algorithm are multiplied by the power of two. This method can reduce the cost of hardware using shifter to replace the multipliers. The image processor contains a two-line-buffer memory to avoid missing pixel. This study improves the main operation of the reference [1] with a circuit hardware sharing technology to increase the logical utility rate. First, the functions of the proposed design were verified by field programmable gate array. Second, the proposed design was synthesized by a Design Compiler toolSecond, this paper synthesizes this design with Design Compiler. Finally, the proposed design used the IC Compiler tool to auto place and route for chip implementationFinally, this paper uses IC Compiler to auto place and route to implement chip. The VLSI architecture of this design is 2.58K gate counts and its core area is 32.2K μm2 synthesized by a TSMC 0.18 μm CMOS processThe VLSI architectures in this design is 2.58K gate counts and its core area is 32.2K um2 synthesized by a 0.18 um CMOS process. It works on the frequency of 200MHz and consumes the power of 3.38mW. Compared with the previous references, this design decreases the gate counts about 11% and maintains high image qualityand maintains image quality in the peak signal to noise ratio.

並列關鍵字

CFA ； Colour compensation ； Colour interpolation ； demosaiking ； Laplacian filter ； Spatial sharpening filter

參考文獻

[9] Shiau, Y. H., Chen, P.Y., and Chang, C. W.: ‘An area-efficient color demosaicking scheme for VLSI architecture’, Int. Journal of Innovative Computing, Information and Control, 2011, 7, (4), pp.1739—1752.

[10] H. A. Chang, and H. H. Chen, “Stochastic color interpolation for digital cameras,” IEEE Transaction on Circuits and Systems for Video Technology, Vol. 17, no. 8, pp. 964-973, Aug. 2007.

[1] Chen, S. L. and Ma, E. D.: ‘VLSI implementation of an adaptive edge-enhanced color interpolation processor for real-time video applications’, IEEE Trans. on circuits and systems for video technology, 2014, 24, (11), pp.1982–1991

[2] M. Parmar and S. J. Reeves , "A perceptually based design methodology for color filter arrays" , Proc. IEEE Int. Conf. Acoust., Speech, Signal Process. , vol. 3 , pp.473 -476 , 2004.

[3] R. Lukac and K. N. Plataniotis , "Color filter arrays: Design and performance analysis" , IEEE Transactions on Consumer Electronics , vol. 51 , no. 4 , pp.1260 -1267 , 2005.