射頻金氧半場效電晶體之模型、特性研究與5.2 GHz低雜訊放大器電路設計

黃建程

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射頻金氧半場效電晶體之模型、特性研究與5.2 GHz低雜訊放大器電路設計

RF MOSFET Modeling, Characterization and 5.2GHz LNA Circuit Design

黃建程 , Masters　　Advisor：蘇炎坤;陳良波　　

英文

模型化；低雜訊放大器；射頻； LNA ； RF ； modeling

Abstract │ Reference (24) │ Times Cited (1) │ Altmetrics

Abstract 〈TOP〉

Parallel Abstract 〈TOP〉

This thesis focuses on the extraction of MOS transistor modeling for RF integrated circuit design and reveals critical characteristics for RF application. Circuit verification had also done. The devices fabricated by 0.18um CMOS technology must be measured precisely using advanced de-embedding techniques first. To facilitate the device applications in the RFIC design, an accurate and powerful MOSFET model is required. The BSIM3 model is a good candidate, having demonstrated accuracy and scalability in the devices characteristics. Besides, BSIM4, as the extension of BSIM3 model, has some major improvements and additions over BSIM3. Comparison between the
BSIM3 model and BIM4 model have been analyzed and discussed. During the procedure of extracting model parameters, the BSIM3 model and BSIM4 model were adopted respectively. The simulation results from DC / RF model show the great agreement with the measured results. Moreover, the noise characteristics of the BSIM3 model and BSIM4 model have been checked and analyzed. Final, a 5.2G low noise amplifier (LNA) conformed IEEE802.11a specification will be designed and the simulation results prove the application of this model for REIC designs. Also, simulated results of LNA is analyzed and discussed.

Reference ( 24 ) 〈TOP〉

[1] P. R. Gray and R. G. Meyer, “Future directions in silicon IC’s for RF personal communications,” Proc. IEEE Custom Integrated Circuits Conference, pp.83-90, May 1995.
連結：
[2] M. Jamal Deen and Tor A. Fjeldly, “CMOS RF modeling, characterization and applications,” World Scientific, 2002.
連結：
[3] L. E. Larson, “Integrated circuit technology options for RF IC’s – present status and future directions,” IEEE J. Solid - State Circuits, vol. 33, pp. 387-399, March 1998.
連結：
[4] C. Wann, F. Assaderaghi, L. Shi, K. Chan, S. Cohen, H. Hovel, K. Jenkins, Y. Lee, D. Sadana, R. Viswanathan, S. Wind, Y. Taur, “High-performance 0.07-um CMOS with 9.5-ps Gate Delay and 150GHz fT,” IEEE Electron Device letters, vol. 18, pp.625-627, 1997.
連結：
[5] Y. Cheng et al., “A Physical and scalable BSIM3v3 I-V model for analog/digital circuit simulation,” IEEE Trans. Electron Device, vol. 44, pp. 277-287, Feb. 1997.
連結：

Times Cited (1) 〈TOP〉

吳孟權(2010)。MOSFET經HC應力後對PSP與BSIM4模型參數影響的分析。臺北科技大學機電整合研究所學位論文。2010。1-96。

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