微波熱效應對鍺通道金氧半場效電晶體之研究

季維均

doi:10.6842/NCTU.2015.00007

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微波熱效應對鍺通道金氧半場效電晶體之研究

A Study on Microwave Thermal Effect for Germanium Channel MOSFETs

季維均 , Masters　　Advisor：簡昭欣　　

英文 DOI： 10.6842/NCTU.2015.00007

鍺；微波退火；金氧半場效電晶體；蕭特基；鎳鍺合金；摻雜析離； Germanium ； Microwave annealing ； MOSFET ； Schottky ； Nickel Germanide ； Dopant segregation

Abstract │ Reference (42) │ Altmetrics

Abstract 〈TOP〉

本論文研究中，首先，我們成功利用微波熱氧化方式成長二氧化鍺製作出三氧化二鋁/二氧化鍺/n型鍺基板之金氧半電容，探討不同微波功率大小與時間所成長的二氧化鍺對電容特性的影響，並且使用電導法來萃取金氧半電容之介面缺陷密度。當微波功率增大或氧化時間增長，等效氧化層厚度隨之增加而介面缺陷密度有下降的趨勢，此結果藉由TEM以及XPS分析驗證。此外，我們探討使用微波後沉積退火在氧氣的環境下對金氧半電容之影響，退火後的介面缺陷密度的值與未退火相比之下降低51%，介面缺陷密度最小值大約為5.9×1011 eV-1cm-2。
其次，我們探討經由微波退火所形成的合金特性表現，為了改善鎳鍺合金的熱穩定性，我們在鎳金屬與n型鍺基板中間加上一層鉑金屬，利用微波退火形成鎳鍺鉑合金的蕭特基接面，我們亦探討鍍上不同厚度的鉑對蕭特基接面特性的影響，發現隨著鉑厚度增加，接面擁有更佳的電性表現，在鉑厚度為10奈米的條件下，擁有最低的理想因子(1.04)、最高的開關電流比(2.1×105)、最高的電子蕭特基能障(0.59 eV)與最低的串聯電阻(9.01Ω)。由低掠角X光繞射分析，在鉑厚度為10奈米條件下形成鎳鍺鉑三元合金。透過原子顯微鏡與掃描式電子顯微鏡，觀察到隨著鉑厚度增加表面粗糙度愈低，有效抑制鎳鍺合金的結塊現象。接著由傳輸線模型萃取出的片電阻以及電阻率，隨著鉑厚度增加，片電阻隨之下降，鎳鍺鉑合金相較於鎳鍺合金的電阻率下降約13%。綜合上述結果，以鉑厚度為10nm的條件下製作通道長度為4μm的蕭特基P型金氧半場效電晶體展現出不錯的電性表現，次臨界擺幅為126mV/dec，元件電流開關比擁有五個數量級，在過驅動電壓為-2.4V及汲極電壓為-2V時，擁有高的驅動電流23.9μA/μm，經由氫氣氮氣混合之熱退火後，元件驅動電流更提升30%。
最後，為了解決費米釘札對於金屬/p型鍺的問題，我們利用磷摻雜離析的方式讓鎳鍺合金/p型鍺接面表現出蕭特基特性。使用微波退火溫度峰值約200°C下形成淺鎳鍺接面(~18nm)與溫度峰值約310°C下進行磷載子活化時可以得到不錯的接面特性，包含最低的理想因子(1.12)、最高的開關電流比(1.7×105)、最高的電洞蕭特基能障(0.58 eV)與最低的串聯電阻(9.12Ω)。因此，在通道長度為5μm的N型金氧半場效電晶體便以此微波條件製作出，元件的次臨界擺幅為197mV/dec.，開關比擁有四個數量級，在過驅動電壓為-2V及汲極電壓為-2V時，驅動電流為3.1μA/μm。此外，我們由原子力顯微鏡以及背面二次離子質譜儀說明低溫微波退火相較於高溫快速退火的優勢在於，低溫活化載子能避免接面因高溫產生鎳鍺合金結塊以及鎳原子擴散產生逆偏電壓相關的漏電流，進而改善接面與元件特性。

Parallel Abstract 〈TOP〉

In this thesis, first, we successfully used microwave thermal oxidation to grow GeO2. We discussed Al2O3/GeO2/n-Ge MOSCAPs characteristics with GeO2 grown by various microwave power and oxidation time, and utilized conductance method to extract the density of interface states. Higher microwave power or longer oxidation time induced EOT increased while Dit value decreased, that was confirmed by TEM and XPS analysis. Besides, we further used the post deposition oxidation microwave annealing in O2 ambient after Al2O3 deposition, the Dit could be improved by 51% compared to w/o PDA treatment. The minimize Dit value was approximately 5.9×1011 eV-1cm-2.
Next, we investigated the metal alloy formation by microwave annealing. In order to enhance the thermal stability of nickel germanide (NiGe), a thin Pt layer was deposited between Ni and n-type Ge bulk and used microwave annealing to fabricate NiGePt/n-Ge Schottky junction, we also investigated the effect of various Pt thicknesses deposition on the performance of the junction. With thicker Pt deposition had better electrical characteristics, the condition of 10nm-Pt deposition exhibited the lowest ideality factor of 1.04, the highest Ion/Ioff ratio of 2.1×105, the highest Schottky barrier height for electron of 0.59eV and the lowest series resistance of 9.01Ω. XRD showed NiGePt2 ternary crystallization with 10nm-Pt deposition. AFM and SEM also demonstrated that surface roughness could be improved with thicker Pt deposition, the agglomeration was suppressed effectively. From TLM, thicker Pt deposition showed lower sheet resistance and the resistivity of NiGePt film was about 13% lower than the NiGe film. Combining above results, we successfully fabricated PMOSFET (L=4μm) with NiGePt S/D by the condition of 10nm-Pt deposition, an excellent substhreshold swing of 126mV/dec, Ion/Ioff ratio of about five orders and high driving current of 23.9μA/μm at VGS-VT = -2.4V and VDS = -2V were achieved. Furthermore, after FGA treatment, the driving current of PMOSFET improved about 30%.
Finally, in order to solve the pinning issue on metal/p-Ge, we used dopant segregation technique to let NiGe/p-Ge junction exhibit Schottky behavior. A shallow (~18nm) NiGe film was formed at Tpeak about 200°C and phosphorous activated at Tpeak about 310°C through microwave annealing, the junction had good electrical characteristics, including the lowest ideality factor of 1.12, the highest Ion/Ioff ratio of 1.7×105, the highest Schottky barrier height for holes of 0.58eV, and the lowest series resistance of 9.37Ω. Combining previous process conditions, we successfully fabricated NMOSFET (L=5μm) with subthreshold swing of 197mV/dec, Ion/Ioff ratio of about four orders and a driving current of 3.1μA/μm at VG-VT = 2V and VD = -2V. Furthermore, we demonstrated the advantages of microwave annealing compared to high rapid thermal annealing by back-side SIMS and AFM. Technique of novel low-temperature microwave activation could be utilized to alleviate alloy agglomeration which was caused by high thermal budget annealing and suppress voltage-dependent generation leakage current which was generated by Ni diffusion, thus enhanced the performance of the junction and the device.

Reference ( 42 ) 〈TOP〉

[1] James M. Early, “Out to Murry Hill to Play: An Early History of transistors,” IEEE Transactions on Electron Device, Vol. 48, No. 11, Nov. 2011.
連結：
[2] G. E. Moore, “Crammimg more components onto integrated circuits,” Electronics, Vol. 38, pp. 114, 1965.
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連結：
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