玻璃基板上之電路設計與實現及其於顯示系統之應用

竹立煒

doi:10.6842/NCTU.2012.00363

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玻璃基板上之電路設計與實現及其於顯示系統之應用

Design and implementation of on-panel circuits for applications in display system

竹立煒 , Ph.D　　Advisor：劉柏村;柯明道　　

英文 DOI： 10.6842/NCTU.2012.00363

液晶顯示器；系統面板；薄膜電晶體；靜電放電防護設計； LCD ； System-On-Panel ； TFT ； ESD Protection Design

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Abstract 〈TOP〉

隨著現今科技的演進，智慧型手機以及平板電腦已將取代筆記型電腦與個人數位助理(Personal Digital Assistant, PDA)裝置，因為其可提供行動網路、多媒體數位與內建全球定位系統(Global Positioning System, GPS)等功能，而這些產品的問世為顯示器與半導體的市場帶來了大幅度的成長，也因此客戶們對於具備高速資料傳輸的產品有了更多的需求，所以顯示裝置具備薄邊框(narrow bezel)、低功耗與高速運算等功能將可大量增加產品的普及性與銷售量。 
為了達到顯示裝置對於薄邊框的需求，液晶顯示器(Liquid Crystal Display, LCD)中的閘極驅動電路(gate driver)使用薄膜電晶體(Thin-Film-Transistor, TFT)設計已成為一個主要的趨勢，因為有成熟的顯示技術、低成本的製程與減少互補式金氧半(Complementary Metal-Oxide-Semiconductor, CMOS)積體電路(Integrated Circuit, ICs)的數量等優點，此外為了降低顯示裝置於靜態畫面顯示時所消耗的功耗，記憶體內嵌於畫素(Memorry-In-Pixel (MIP)的概念也被提出並使用薄膜電晶體所設計，然而設計薄膜電晶體的電路相對於CMOS電路主要面對到較低的載子傳輸能力以及高電壓驅動導致穩定度下降的兩個重要挑戰，而為了降低較低載子傳輸能力的限制，薄膜電晶體在佈局時會使用較大的面積推動面板內部的負載，但也不可避免造成電路具有較大的寄生(parasitic)效應，再加上薄膜電晶體電路的耐久度也是一個需要解決的問題，因為當薄膜電晶體經過長期電壓的施加，薄膜電晶體的主動層會產生大量缺陷(defects)進而使電晶體的臨界電壓偏移減少了顯示產品的耐久度，所以前述的兩項因素為薄膜電晶體電路的主要設計挑戰。此外大型積體電路(Large Scale Integration, LSI)接合於顯示面板是為了減少IC的腳位以及增加處理射頻(Ratio Frequency, RF)訊號的能力，然而射頻前段電路是與外部天線或濾波器所連接，所以其必然需要靜電放電(ElectroStatic Discharge, ESD)防護電路的放置，但靜電放電防護元件無可避免的會讓輸入與輸出的銲墊(Pad)增加額外寄生的效應，因此設計靜電放電防護元件於面板上的電路也是一個重要的挑戰，即同時達到最高靜電放電的耐受度以及最小射頻訊號的損失。 
總結前述的電路設計的挑戰即為本研究論文的主題:設計與實現玻璃基板上之電路及其於顯示系統的應用，本論文的章節包括：(1) 設計可消除電晶體臨界電壓的閘極驅動電路於非晶矽薄膜製程、(2) 設計低功率閘極驅動電路以非晶矽薄膜製程於薄邊框面板的應用、(3) 類比畫素記憶體電路以低溫多晶矽製程於低功耗顯示器的應用、 (4) 電感觸發觸發矽控整流器的靜電放電防護電路以65奈米CMOS製程於60GHz低雜訊放大器的應用、(5) 設計雙波段靜電放電防護電路於毫米波電路的應用。
本論文第二章提出一種新型的閘極驅動電路並成功以非晶矽薄膜電晶體設計與製作於3.8吋WVGA(480xRGBx800)規格的面板，此提出之電路利用電晶體臨界電壓消除之方式，使閘極驅動電路的輸出上升時間(Rise Time)減少了24.6%，進而使其可應用於高解析度之顯示器。本論文第三章利用四個時脈(Clock)訊號設計閘極驅動電路，使得推升電晶體同時具備輸出充電與放電的功能，進而使電路的佈局面積有效的縮小並可於薄邊框的顯示器應用，此外因為減少了時脈訊號的工作週期(Duty Cycle)，所以此提出之電路可以減少靜態功率的消耗，而電路的掃描方向也只需透過切換兩個直流訊號即可達到反向顯示的功效，此所提出之電路已成功展示於WXGA(1440xRGBx800)規格的面板且通過合作公司的穩定度測試。
本論文第四章提出兩種多晶矽薄膜電晶體類比記憶體電路於低功耗應用的液晶顯示器之設計，此電路將反轉畫素電壓透過互補式源極追隨器(Source Follower)使資料訊號可儲存於電容上，並將顯示靜態影像的畫框時間由60Hz降低至3.16Hz，而輸出的電壓的衰減也小於0.1V於1到4V的資料訊號輸入中，本論文亦提出一種可補償電晶體臨界電壓的設計，達到減少源極追隨器的輸出電壓對於電晶體臨界電壓的相依性。
本論文第五章提出使用電感加速矽控整流器導通速度的靜電放電防護電路，而電感的感值與矽控整流器的寄生電容可設計共振於射頻電路所操作的頻率，進而降低射頻訊號的損耗(Loss)，而此提出之射頻靜電放電防護電路已驗證於65奈米CMOS製程並操作於60GHz，且為了射頻接收器的射頻特性和靜電放電防護能力的證實，所提出的電感觸發矽控整流器靜電放電防護電路已成功應用於60GHz低雜訊放大器中並獲得良好的成果。本論文第六章提出雙波段(24GHz與60GHz)靜電放電防護電路，此電路由二極體、矽控整流器、P型電晶體與電感所組成，而為了驗證雙波段的射頻特性與靜電放電的防護能力，所提出之電路已成功應用於雙波段低雜訊放大器中，量測的結果展示了超過2.75kV的人體放電模式(Human Body Model, HBM)且雙波段射頻的特性也僅有些微的損耗。
第七章總結本論文的研究成果，並提出數個接續本論文研究方向的研究題目。本論文所提出的各項新型設計，皆已搭配面板整合或實驗晶片加以驗證。此外本研究有數篇國際期刊與國際研討會論文發表，並有數項創新設計已提出中華民國及美國專利申請。

Parallel Abstract 〈TOP〉

With current technology advancements, smart phones and tablet computers are fast becoming a viable alternative to PDAs and laptops, offering features such as mobile internet applications, multi-media functionality, and inbuilt GPS capabilities. The emergence of these products brings the progressive growing of display market. Therefore, display devices with narrow bezel, low power consumption, and high speed data capabilities are gaining the sale volume and popularity. 
For the narrow bezel demands of display devices, gate driver circuit using thin-film-transistor (TFT) has become a main stream for the liquid crystal display (LCD) due to the mature manufacturing, low-cost processing, and reducing of complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs). Furthermore, the design of memory-in-pixel (MIP) using TFT is as well as proposed to meet the low power consumption of mobile displays, which provided a low power standby mode for continuous display of static images. Nevertheless, design of TFT driver encounters two main challenges which are the lower field-effect mobility and the reliability issue under high voltage stress as compared with CMOS transistors. In order to alleviate the low mobility restriction, the larger width of the main driving TFT is required to drive the panel, however it accompanies with large parasitic effects inevitably. In addition, the reliability issue of the TFT drivers is as well as a notable challenge. While TFT suffers long term high voltage stress, the defect-state creation will cause threshold voltage shifts to decrease the life time of the driver. Consequently, these characteristics increase the design challenge of TFT driver circuits. Besides, large scale integration (LSI) mounted on-panel area is primarily used to minimize footprint of the IC and suited to handling high-frequency (RF) signals. However, since the RF front-end circuits connect the RF transceiver to the external antenna or band-select filter, they must need electrostatic discharge (ESD) protections. The ESD protection devices at the I/O pads inevitably cause parasitic effects on the signal path and lead to the design challenge for on-panel RF circuits, which is to achieve the highest ESD robustness with the smallest RF performance degradation.
   The aforementioned design challenges of on-panel circuits for applications in display system form the motivation of this dissertation. The research topics of this dissertation including: (1) integrated gate driver with threshold voltage drop cancellation in amorphous silicon (a-Si) technology, (2) low power gate driver in a-Si technology for narrow bezel panel application, (3) analog pixel memory in low temperature poly silicon (LTPS) technology for low power display, (4) ESD protection design for 60GHz low noise amplifier (LNA) with inductor-triggered silicon-controlled rectifier (SCR) in 65nm CMOS process, and (5) dual-band ESD protection for 24/60 GHz millimeter-wave circuits. 
In chapter 2, a new integrated gate driver on array (GOA) has been successfully designed and fabricated by amorphous silicon (a-Si) technology for a 3.8-inch WVGA (480xRGBx800) TFT-LCD panel. With the proposed threshold voltage drop cancellation technique, the output rise time of the proposed integrated gate driver can be substantially decreased by 24.6% for high resolution display application. In chapter 3, with utilizing four clock signals in the design of GOA, the pull-up transistor has ability for both output charging and discharging, and layout size of the proposed gate driver can be narrowed for bezel panel application. Moreover, lower duty cycle of clock signals can decrease static power loss to further reduce the overall power consumption of the proposed gate driver. The scan direction of the proposed gate driver can be adjusted by switching two direct control signals to present the reversal display of image. Additionally, the proposed gate driver has been successfully demonstrated in a 4.5-inch WXGA (1440xRGBx800) TFT-LCD panel and passed reliability tests of the supporting foundry. 
In chapter 4, two types of analog memory cells realized in 3m LTPS technology are proposed to achieve low power application for thin film transistor liquid crystal displays (TFT-LCDs). By employing the inversion signal in the storage capacitor with complementary source follower, the frame rate to refresh the static image can be reduced from 60Hz to 3.16Hz with the output decay less than 0.1V under the input data from 1V to 4V. To further diminish threshold voltage drop from source follower structure, a compensation technique is implemented to the proposed analog memory cells. 
In chapter 5, an SCR device assisted with an inductor is proposed to improve the turn-on efficiency for ESD protection. Besides, the inductor can be also designed to resonate with the parasitic capacitance of the SCR device at the selected frequency band for RF performance fine tuning. Experimental results of the ESD protection design with inductor-triggered SCR in a nanoscale CMOS process have been successfully verified at 60GHz frequency. To verify the RF characteristics and ESD robustness in the RF receiver, the inductor-triggered SCR has been applied to a 60GHz low-noise amplifier (LNA). In chapter 6, dual-band ESD protection cell is proposed for 24/60 GHz ESD protection. The proposed cell consisted of a diode, a silicon-controlled rectifier (SCR), a PMOS, and inductors. To verify the dual-band characteristics and ESD robustness for the RF receiver, the proposed ESD protection circuit had been applied to a 24/60 GHz low-noise amplifier (LNA). Measurement results present over 2.75kV human-body-model (HBM) ESD robustness with little RF performance degradation. 
Chapter 7 summarizes the main results of this dissertation. Some suggestions for the future works are also addressed in this chapter.
In this dissertation, several novel designs have been proposed in the aforementioned research topics. Measured results of the integrated panels and fabricated test chips have demonstrated the performance improvement. The achievements of this dissertation have been published or submitted to several international journal and conference papers. Several innovative designs have been applied for patents.

Reference ( 92 ) 〈TOP〉

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