不同介電質的平面式及閘極環繞式氮化矽快閃記憶體之寫入/抹除/保存模擬

Numerical Simulation of Program/Erase/Retention in Planar and GAA SONOS with Different Dielectrics

蔡德宏(Te-Hung Tsai)

指導教授 ： 汪大暉

國立交通大學/電機學院/電子工程系所/碩士(2015年)

https://doi.org/10.6842/NCTU.2015.00725

摘要

本篇論文中，吾人建立了一個較完整且一致的一維寫入/抹除/保存模型，透過吾人所建立的模型，可以快速地分析改變介電質材料以及結構對寫入/抹除區間(program/erase window)的影響。根據吾人的模型，使用閘極環繞式(Gate-All-Around)的結構可以改善寫入/抹除區間，而在此基礎上再使用氮氧化矽作為穿隧介電層，可以進一步改善寫入/抹除區間。但使用高介電係數之上介電層搭配金屬閘極(high-dielectric constant top oxide and metal gate)，才是對於改善寫入/抹除區間的關鍵方法。吾人的模型重現了抹除操作時，臨界電壓反轉之現象，及提出減少閘極電子注入有助於改善此反轉現象。垂直方向及水平方向保存流失亦在本論文中討論。經由吾人的模擬發現，使用氮氧化矽作為穿隧介電層不利於垂直方向之電荷保存。而水平方向的電荷移動對於臨界電壓值的影響不如垂直方向電荷流失所造成的影響。

關鍵字

氮化矽快閃記憶體 ； 元件模擬 ； 模型

並列摘要

In this thesis, we developed a complete and consistent program/erase/retention model which can evaluate the performance boosted by changing structure and dielectrics. According to our model, the program/erase window can be improved by using Gate-All-Around(GAA)structure, and it can be further improved by using SiON as tunneling dielectric. However, usinghigh-k metal gate(HKMG)is the crucial way to improve it. Our modelreproduceserase Vthturn-around behavior, and suggests that reducing gate electron injection contribute to improve it. Retention loss via vertical and lateral direction are also evaluated. It suggests thatusingSiON as tunneling dielectric goes against retention characteristic via vertical direction. The effect of charge lateral migration is evaluated and it is less important to charge vertical loss according to oursimulation result.

並列關鍵字

SONOS memory ； device simulation ； model

參考文獻

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