以行為模型建立交換電容式積分器之非理想現象及準確時間響應的研究

陳柏仁

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以行為模型建立交換電容式積分器之非理想現象及準確時間響應的研究

On Behavioral Modeling of Switched-Capacitor Circuits with Non-Ideal Effects and Accurate Timing Response

陳柏仁 , Masters　　Advisor：劉建男　　

繁體中文

交換電容式積分器；三角調變積分器；行為模型； sigma-delta modulator ； Switched-Capacitor Circuit ； Behavioral Model

Abstract │ Reference (18) │ Altmetrics

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In order to reduce the simulation time of analog circuits, the simulation model needed to be raised to higher abstract level. Therefore, the ideal behavioral model of a switched-capacitor integrator has been developed by using Verilog-A Hardware Description Language in this thesis.
In our ideal model, the behavior of integrator in time-domain has been described more carefully to make our model more close to the real circuits. In the case of non-ideal effect in the integrator, not only the DC Gain, DC Level Offset, External Slew Rate and Switch Thermal Noise have been considered. We also consider several important non-ideal effects like Settling Time of integrator, Operational Amplifier Noise and Supply Voltage Variation. We build a standard extraction by using bottom-up method to extract those non-ideal parameters. After annotating those non-ideal parameters in to our ideal model, then the behavior of our developed model can be more close to real circuits.
In this thesis, we use a second-order sigma-delta modulator, which includes two switched-capacitor integrators, to verify our developed model. According to the experimental results, the behavior of our model can perform more close to the real circuits in time-domain. And due to the accurate time-domain behavior of our developed model, the behavior in frequency-domain can also fit the exact behavior of real circuits. The most important thing is that using our developed model can greatly reduce the simulation time instead of the traditional simulation methods.

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[3] Miller, I.; FitzPatrick, D.; Aisola, R.;” Analog design with Verilog-A”, Verilog HDL Conference, 1997., IEEE International, 31 March-2 April 1997, Page(s):64 - 68
連結：
[7] P.E.Allen, D.R.Holberg “CMOS Analog Circuit Design”2nd ed. New York Oxford, 2002 Page(s): 698-699
連結：
[10] B.E.Boser, B.A.Wooly “The Design of Sigma-Delta Modulation Analog to Digital Converters” Solid-State Circuits, IEEE Journal of, Dec. 1988, Page(s): 1298 – 1308
連結：
[14] Wern Ming Koe; Jing Zhang; “Understanding the effect of circuit non-idealities on sigma-delta modulator” Behavioral Modeling and Simulation, 2002. BMAS 2002. Proceedings of the 2002 IEEE International Workshop on, Page(s):94 – 101, 6-8 Oct. 2002
連結：
[16] C. T. CHUANG, STUDENT MEMBER, IEEE “Analysis of Settling Behavior of an Operational Amplifier”IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-17, NO. 1, FEBRUARY 1982
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