控制峰值溫度與電壓降之三維積體電路固定框架平面規劃

由於積體電路的應用愈來愈廣泛使用在人類的生活中，因此積體電路的功能需求也愈來愈龐大，三維積體電路(3D ICs)便是在這股趨勢下產生。有別於一般所使用的二維積體電路(2D ICs)，三維積體電路增加了垂直方向的連結，也因為三維積體電路是由多個二維積體電路堆疊而成，所以三維積體電路可以利用不同製程的二維積體電路製造，這便是三維積體電路異質整合的優勢。三維積體電路雖然有許多優於二維積體電路的特性，但仍有許多待解決的問題。隨著供應電壓的降低與頻率的增加，峰值溫度(peak temperature)與峰值電壓降(peak IR-drop)的問題愈來愈明顯，加上在三維積體電路的結構中，有低熱導率(thermal conductivity)的材質在其中，因此三維積體電路的溫度問題更加嚴重。本篇論文提出了一個流程，可以有效地控制三維積體電路的溫度與電壓降。我們在平面規劃(floorplanning)階段擺放電路區塊(blocks)，並且考量固定框架(fixed-outline)的限制，讓我們在有限的空間做適當的使用。為了防止在擺置(placement)或繞線(routing)階段，電路區塊因為塞滿散熱型矽晶穿孔(thermal TSVs)而無法做繞線，我們提出的流程會提早考量訊號型矽晶穿孔(signal TSVs)的面積。實驗結果可以得知提前在平面規劃階段考量熱與電壓降的問題，較在後平面規劃(post-floorplanning)階段才考量有效，但會犧牲部分線長(wirelength)來控制峰值溫度與電壓降。

關鍵字

三維積體電路；平面規劃；散熱；電壓降；散熱型矽晶穿孔；去耦合電容

並列摘要

As integrated circuits (ICs) are widely used in humans’ daily life, the number of functions of ICs is required to be more. Three dimensional ICs (3D ICs) are born with the trend. The difference between 3D ICs and traditional 2D ICs is that, 3D ICs are added the property of the vertical connection, which is made by through-silicon-vias (TSVs). 3D ICs have the feature of heterogeneous integration, which is that the dies with different manufacturing processes can be integrated to one IC. Although 3D ICs have some powerful advantages comparing with 2D ICs, 3D ICs have two critical problems. One is heat issue, another is IR-drop. Due to the increasing number of circuit blocks and the effect of low thermal conductivity of 3D ICs, the heat is difficult to be dissipated. IR-drop issue is due to the increasing frequency and decreasing power supply voltage. We propose a design flow in the floorplanning stage with fixed-outline constraints, which can control the peak temperature and the peak IR-drop of 3D ICs effectively. Besides, for considering routability, signal TSVs are added in advance to reserve area. According to the experimental results, the proposed flow can control the peak temperature and the peak IR-drop under given constraints. Comparing with the previous work in the post-floorplanning stage, the proposed flow can reduce peak temperature about 40%. Although the total wirelength increases, the peak temperature and the peak IR-drop can be controlled effectively.

並列關鍵字

3D ICs ； floorplanning ； thermal ； ir-drop ； thermal tsv ； decoupling capacitors

參考文獻

[5] Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, and Chien-Nan Jimmy Liu, “ILP-based Inter-die Routing for 3D ICs,” in Proceedings of Asia and South Pacific Design Automation Conference, pp. 330-335, 2011

[2] International Technology Roadmap for Semiconductors, 2009

[4] Jian-Qiang Lu, “3D Hyperintegration and Packing Technologies for Micro-Nano Systems,” in Proceedings of IEEE, pp. 18-30, 2009

[8] Sungjun Im and K.Banerjee, "Full Chip Thermal Analysis of Planar (2-D) and Vertically Integrated (3-D) High Performance ICs," International Electron Devices Meeting, pp. 727-730, 2000

[11] Shiyou Zhao, Kaushik Roy, and Cheng-Kok Koh, "Decoupling Capacitance Allocation and Its Application to Power-Supply Noise-Aware Floorplanning,” in Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 1, pp. 81-92, 2002

國際替代計量

控制峰值溫度與電壓降之三維積體電路固定框架平面規劃

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