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高性能之低溫多晶矽薄膜電晶體及其應用

High Performance Poly-Si TFTs Using Ultra-thin HfSiO(subscript x) Gate Dielectric and Applications

摘要


結合超薄氧化矽鉿(HfSiO(下標 x))及金屬閘極(TiN)之多晶矽薄膜電晶體,其次臨界擺幅可達193 mV/dec,其製程溫度最高為700℃,適合應用於單片式三維積體電路(Monolithic 3D-IC)及Silicon-on-Glass(SOG)。長通道多晶矽薄膜電晶體有較多晶粒邊界而影響其載子傳遞,因此有較高的汲極(Drain)電流雜訊密度(S(下標 ID))及較小的指數因數(γ),同時在其能隙狀態密度也可證實同樣的結果。此元件在高效能電路設計及應用發展上提供一個解決方案。

並列摘要


High performance Poly-Si TFTs using an ultra-thin High-κ metal gate stack with a subthreshold swing (SS) of 193 mV/dec when operating at room temperature and its maximum thermal budget around 700℃ are readily compatible with monolithic three-dimensional integrated circuits (3D-ICs) and silicon-on-glass (SOG) applications. Long-channel TFTs have a higher drain current noise spectral density, S(subscript ID), and a smaller exponential frequency factor (γ) due to the influence of numerous grain boundaries on carrier transport, as confirmed by gap state density extraction. These devices may pave the way for high performance circuit designs and applications such as monolithic 3D-ICs, SOG, and AMOLED technology.

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