- 學位論文
基於RISC-V開源處理器架構的Avalon匯流排橋接器之設計與實現
Design and Implementation of Avalon Bus Bridge Based on RISC-V Open-Source Processor Architecture
摘要
本論文目的是在Intel公司推出的DE系列FPGA開發平台上，實現一個RISC-V系統。首先本論文設計一個Picorv32處理器與Avalon bus連接的橋接器，使Picorv32處理器能夠透過Avalon匯流排存取Qsys系統上的記憶體和周邊(Peripheral)，並且在DE2-115開發平台上對此RISC-V系統進行模擬、驗證和展示。 本論文包含了軟硬體的設計與開發流程，在軟體上，有編譯器工具鏈和指令集的選用、連結器腳本的修改、執行檔的格式轉換、記憶體初始化和燒錄；在硬體上，設計了Picorv32處理器與Avalon匯流排之間的橋接器，並對橋接器做出完整的時序分析和波形驗證，同時也設計了基於硬體架構的程式下載器，用來幫助下載程式到記憶體中。 在論文的最後比較了Picorv32和Nios II處理器的性能測試以及硬體上的邏輯資源消耗，從實驗結果證明Picorv32處理器的設計架構是優於Nios II/e處理器架構，將有機會取代Nios II/e處理器成為系統的核心處理器。
並列摘要
The purpose of this thesis is to implement a RISC-V system on the DE series FPGA development platform released by Intel Corporation. Firstly, this thesis designs a bridge connector that connects the Picorv32 processor with the Avalon bus, enabling the Picorv32 processor to access memory and peripherals in the Qsys system through the Avalon bus. The design is then simulated, validated and demonstrated on the DE2-115 development platform. The thesis includes both hardware and software design and development processes. On the software side, there are compiler tool chains, instruction set selection, modification of linker scripts, format conversion of executables, memory initialization and burning. On the hardware side, the design of the bridge connector between the Picorv32 processor and the Avalon bus is presented, with a complete timing analysis and waveform verification, and a hardware-based program downloader is also designed to help download programs into memory. At the end of the thesis, a performance comparison is made between the Picorv32 and Nios II processors, as well as a logic resource consumption comparison in hardware. The experimental results prove that the design architecture of the Picorv32 processor is superior to that of the Nios II/e processor, and has the potential to replace the Nios II/e processor as the core processor of the system.