- 學位論文
具有相位對齊之高解析度脈衝寬度調變延遲鎖定迴路
A High Resolution DLL-based Pulse Width Modulation Circuit with Phase Alignment
摘要
由於現今在積體電路系統中已經廣泛的應用系統晶片設計概念，且市場對於高效能系統單晶片的需求日漸增長，為了整合更多功能，時脈合成或是倍頻基本已經成為晶片內部中不可或缺的功能之一。且至今電路系統中的時脈訊號也愈來愈快，在晶片內部的非理想效應會使相位產生誤差以及延遲，這可能會嚴重影響整個系統的效能，因此數位系統電路整合的同步性也變得相當重要。隨時傳統常見的頻率合成器時常使用鎖相迴路（Phase-Locked Loop，PLL）設計，不過延遲鎖定迴路（Delay-Locked Loop，DLL）本身的時脈抖動(Jitter)以及穩定度方面表現相比於鎖相迴路(PLL)要好。一般而言，鎖相迴路(PLL)系統中含一電壓控制振盪器(Voltage Controlled Oscillator)，而此電路常會無法避免的抖動雜訊累積(Jitter accumulation)，而延遲鎖定迴路(DLL)中的電壓控制延遲線(Voltage-Controlled Delay Line，VCDL)不會將輸入的雜訊累積在其中，進而使得鎖相迴路(PLL)之雜訊抗擾性低於延遲鎖定迴路(DLL)。且延遲鎖定迴路(DLL)之迴路濾波器僅需要一階的電容，不同於鎖相迴路(PLL)需要二階以上的複雜濾波器來使系統穩定，如若設計不當可能會導致系統不穩定甚至失鎖。所以延遲鎖定迴路(DLL)此方面不僅降低了晶片面積，其系統容易穩定，也具有容易設計的特性。延遲鎖定迴路(DLL)已被廣泛地運用在許多需要時脈操作的電路上，如同步動態記憶體(SDRAM) 、數位信號處理器(DSP)、類比數位轉換器(ADC)等等，都可以使用延遲鎖定迴路來提供一個穩定的系統時脈，使電路可以達到預期的性能。 我們在架構中包含相位偵測器(Phase Detector，PD)、充電幫浦(Charge Pump，CP)、迴路濾波器(Loop Filter，LF)以及電壓控制延遲線(VCDL)，而為了提高延遲時間的解析度，運用了相位內插的方式。在系統鎖定後，系統後方相位內插電路(Interpolator)在電壓控制延遲線(VCDL)的延遲級中不同的相位之間做內插，來產生不同的相位，再經過控制選擇及相位比較來合成出不同的脈衝寬度的輸出，令此延遲鎖定迴路(DLL)可運用在脈衝寬度調變(PWM)，提高實用性。我們所提出的延遲鎖定迴路(DLL)架構採用台積電0.18-μm CMOS製程來實現，在工作電壓是1.8-V下，操作頻率為100-MHz，最小解析度為11.25˚，整體功耗為2.07 mW。
並列摘要
Due to the frequent use of the current chip, process technology is also more advanced, the clock signals in circuit system has been faster, and non-ideal effects within the chip will produce phase error and delay. This problem can seriously affect the overall system performance. Therefore, the clock synchronization of the digital system circuit becomes more important, especially in high-speed computing systems, the clock skew will be an important factor to determine the performance of the system. Clock synchronization technology usually through the phase-locked loop (PLL) and delay-locked loop (DLL) to eliminate the clock offset, increase the circuit stability, can produce a stable output oscillation frequency, and reduce product costs to increase product competitiveness. The jitter and stability of DLL is better than PLL. In general, a Voltage Controlled Oscillator (VCO) is included in a phase-locked loop (PLL) system, which is often unavoidable for Jitter accumulation, and Voltage-Controlled Delay Line (VCDL) in the Delay Lock Loop (DLL) doesn’t accumulate input noise, making the noise immunity of the phase-locked loop (PLL) lower than the delay-locked loop (DLL). And the delay-locked loop (DLL) circuit’s filter only requires a first-order capacitor, unlike the phase-locked loop (PLL) requires more than two-order complex filters to stabilize the system, if not properly designed may lead to system instability or even unlock. Therefore, the delay-locked loop (DLL) not only reduces the chip area, its system is easy to stabilize, but also has the characteristics of easy design.DLL has been widely used in the clock circuits, such as synchronous dynamic RAM (SDRAM), digital signal processor (DSP), analog-to-digital converter (ADC), etc., All of them can use the DLL to provide a stable system clock, so that the circuit can achieve the desired performance.. In this paper,we include phase detector (PD), Charge Pump(CP), Loop Filter (LF), and Voltage Control Delay Line (VCDL) in the architecture, and use phase interpolation to improve the resolution of delay. After the system is locked, the rear phase interpolator circuit (PI) interpolates between different phases in the delay stage of the voltage control delay line (VCDL) to produce different phases, and then synthesizes the output of different pulse widths by controlling selection and phase comparison, so that this delay-locked loop (DLL) can be used in pulse width modulation (PWM) to improve practicality. The proposed DLL architecture is based on 0.18μm 1P6M CMOS process with an operating voltage of 1.8 V, input reference frequency is 100 MHz, the minimum resolution is 11.25 degrees and the power consumption is 2.07 mW.