摘要
積體電路的設計與製程在近幾年快速的成長，導線互連、成本、熱、良率等問題造成二維積體電路發展上的瓶頸。三維積體電路使用了直通矽晶穿孔(Through-silicon via, TSV)技術，將平面電路以堆疊的方式透過矽晶穿孔互相連接，讓電路間連線密度提升，進而可縮小外觀尺寸、提高速度、降低消耗功率。 本論文提出一套三維平面規劃的方法，以模擬退火為基底，用局部最佳合併演算法搭配放鬆波蘭式決定電路元件(Modules)的擺放位置，接著透過配對的方式選擇直通矽晶穿孔，最後使用制約式最長共同子序列對整體電路做全壓縮、半壓縮，並計算整體的半周線長。 本研究以GSRC與MCNC Benchmark做為測試電路，實驗結果顯示出對電路元件做整體壓縮或半壓縮能更有效的減少整體線長。
並列摘要
As the complexity of integrated circuits have grown rapidly in recent years, the interconnect delay, cost, heat and yield rate became the bottleneck of traditional 2D architecture. The emerging 3D architecture used the technique of Through-Silicon-Via (TSV), by stacking the circuits and connecting each layer with TSVs. It can improve interconnect density, reduce form factor, increase speed and reduce power consumption. In this thesis, we propose an efficient methodology of 3D floorplanning. Firstly, we use a greedy merging approach to work with relax Polish expression based on simulated annealing algorithm. Secondly, we apply a matching method to choose the TSVs. Finally, we use constrained longest common subsequence (CLCS) to perform full-compact or half-compact on the modules and then calculate the total wire length. GSRC and MCNC Benchmark are used as test circuits in out experiments. The experimental results show that our approach works efficiently and it can further reduce the total wire length.