應用於台灣期貨市場基於場效可程式化邏輯閘陣列加速之高頻交易系統

An FPGA-based High-frequency Trading System on Taiwan Futures Market

高翊傑(Yi-Chieh Kao)

指導教授 ： 馬席彬

國立清華大學/電機資訊學院/電機工程學系所/碩士(2021年)

摘要

高頻交易以快速反應市場變化來從中獲取利潤。因此透過減少系統延遲以及提高吞吐量，可以提升高頻交易者的日淨利。本篇論文針對台灣期貨交易過程設計基於場效可程式化邏輯閘陣列加速之高頻交易系統。此系統實現10G乙太網路實體收發器、客製化網路分層的解包與封包、部分台灣期貨市場訊息的編碼與解碼、期貨市場商品五檔價量的管理以及簡易的高頻交易策略。乙太網路實體收發器採用156.25兆赫時脈傳輸64位元的資料寬度。接收端能夠辨認並解析位址解析協定、使用者資料報協定與傳輸控制協定的乙太封包，並且提供傳輸控制協定的連線功能。本篇論文針對此系統的硬體測試，使用台灣真實期貨交易環境來驗證系統在市場行情解析上的正確性以及與期交所連線並策略觸發下單的功能。經實驗結果得到設計與實現的高頻交易系統無論在日盤或夜盤皆能準確解析市場行情資訊並得到特定商品的五檔價量，並且當觸發策略時能夠向期交所委託下單。除此之外，透過乙太封包內時間戳比較進出封包的時間差得到從封包解析到觸發下單一整條完整交易路徑的延遲僅約500奈秒，相比於軟體程式交易系統以微秒等級計算的延遲，效能提升近100倍以上。

關鍵字

高頻交易 ； 硬體加速 ； 場效可程式化邏輯閘陣列 ； 期貨

並列摘要

High-frequency trading (HFT) systems require extremely low latency in response to market updates to make profits. Therefore, reduce the overall system latency and increase the throughput can increase the daily net profit of high-frequency traders. In this thesis, an FPGA-based high-frequency trading system is designed and implemented. The proposed system implements 10G ethernet physical interface, customized network stack parsing and packaging, partial financial protocol decoding and encoding, futures market order book handling and customized trading strategy. A 156.25 MHz clock is used to clock the 64-bit datapath of ethernet physical transceiver and receiver. For network stack decoding, the system can identify and analyze the ethernet packets of the address resolution protocol (ARP), user datagram protocol (UDP), transmission control protocol (TCP), and provides the functionality of TCP connection. The proposed system has connected to the real futures trading environment to verify the correctness of the functionality of market data parsing and order management processing. Based on the verification and evaluation on field programmable gate array (FPGA), the proposed system can accurately analyze the market information and obtain the fifth-order of specific product regardless of the trading time, and issue an order when the trading strategy is triggered. An aggregated latency of 500 ns is measured. This result in a hundred-time more efficacy than a typical software-based HFT system.

並列關鍵字

FPGA ； HFT ； Futures ； Acceleration ； Hardware

參考文獻

[1] “Taiwan Futures Exchange (TAIFEX), https://www.taifex.com.tw/enl/eIndex.

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