- 學位論文
除電參數分析及實驗設計於晶圓蝕刻後之偏移量改善研究
Analysis and Study of Electrostatic Chuck (ESC) For Etched Wafer Shift Improvement
摘要
在蝕刻晶圓生產過程中，以靜電式晶圓座(Electrostatic Chuck , ESC)將晶圓吸附於腔體內，其原理是利用靜電吸附力來固定晶圓，以外加電極及電壓來產生靜電吸附的功用，當蝕刻完畢後會施以除電(Dechuck)程序之反向電壓來消除ESC與晶圓間的靜電電荷，以利電性中和，能讓頂針能順利將晶圓頂起。若是反向電壓或其他環境參數未達到平衡時，容易造成晶圓拖片、滑片甚至破片的問題產生。 本研究以半導體蝕刻機型為實驗機台，利用魚骨圖分析找出可能造成晶圓偏移量的因子，再由田口法設計七個可控因子及兩個實驗水準作八組實驗。從實驗結果研究分析影響晶圓偏移量的參數，進行調整相關的參數，使晶圓的偏移量能達到最小化。本研究實驗分為晶圓吸附靜電消除，頂起晶圓之角度軸與前後軸兩方面，實驗數據結果有明顯的改善，整體晶圓偏移量警示由27%降至6.5%，減少失誤的次數和製程時間，減少相對的成本。
並列摘要
In the process of etching wafers, electrostatic wafer holders (ESC) are used to fix the wafers into the etching chamber. The principle is to use electrostatic adsorption to fix the wafers by applying electrodes and voltage to generate electrostatic adsorption. After the etching is completed, the reverse voltage of the Dechuck procedure will be applied to eliminate the electrostatic charge between the ESC and the wafer. If the reverse voltage or other environmental parameters do not reach equilibrium, it may easily cause problems such as wafer dragging, sliding and even chipping. In this study, a semiconductor etching machine is used as an experimental equipment. Fishbone diagram analysis is used to find the factors that may cause wafer offset. Then, the Taguchi method is used to design seven controllable factors and two experimental levels for eight groups of experiments. By analyzing the parameters that affect the wafer offset from the experimental results, the experiments adjust the relevant parameters of Dechuck process to minimize the wafer offset. The experiment process is divided into wafer adsorption static elimination, lifting the wafer's angular axis and front and rear axis. The experimental results have improved significantly. The overall wafer offset warning has been reduced from 27% to 6.5%. This etched wafer shift improvement study reduces process time and relative costs. Ultimately increased machine productivity.