簡易檢索 / 詳目顯示

研究生: 李偉豪
論文名稱: 應用於棘波分類之硬體架構實現
Hardware Implementation for Spike Sorting
指導教授: 黃文吉
學位類別: 碩士
Master
系所名稱: 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年: 2012
畢業學年度: 100
語文別: 中文
論文頁數: 50
中文關鍵詞: 可程式化系統晶片棘波分類主成分分析GHAFCMFPGA
英文關鍵詞: system on programmable chip, spike sorting, principal component analysis, generalized Hebbian algorithm, fuzzy c-means algorithm, FPGA
論文種類: 學術論文
相關次數: 點閱:69下載:6
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 本論文針對快速棘波分類設計了一套專用的架構,並於硬體中實現此架構。本論文採用Generalized Hebbian Algorithm (GHA) 來擷取棘波的特徵值,搭配Fuzzy C-Means (FCM) 演算法將擷取到的棘波特徵值進行分類。GHA演算法可高速計算主成分特徵值供後續分群演算法進行運算,同時利用FCM演算法對於初始質心選取好壞不敏感的特性可獲得較佳的分類結果。為了減少硬體資源的消耗,GHA架構中在計算調整不同組權重值時皆共享相同一塊計算電路,而FCM採用逐步增量計算權重係數與質量中心點,這可以避免原本需要大量儲存空間儲存權重係數矩陣所造成的空間消耗。因此,本論文所提出的架構同時擁有低area cost與高輸出產量的優點。為了驗證本論文所提出的架構有效性,我們於現場可程式邏輯閘陣列 (Field Programmable Gate Array , FPGA) 中實作出本架構,並於嵌入式System-On-Programmable-Chip (SOPC) 平台中進行實際效能量測。實驗結果證明針對棘波分類本論文所提出的架構同時具有低判斷錯誤率、低area cost與高速計算的優點。

    This paper presents a novel architecture for fast spike sorting. The architecture is based on Generalized Hebbian Algorithm (GHA) and Fuzzy C-Means (FCM) algorithm. The GHA are used for feature extraction and the FCM are used for clustering. To show the effectiveness of the circuit, the proposed architecture is physically implemented by Field Programmable Gate Array (FPGA). It is embedded in a System-On-Programmable-Chip (SOPC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for at-taining low classification error rate, low area costs and high speed computation.

    附圖目錄 vi 附表目錄 viii 第一章 緒論 1 1.1 研究背景與動機 1 1.2 研究目的與方法 2 第二章 基礎理論與背景介紹 5 2.1 文獻探討 5 2.2 GHA演算法 7 2.3 FCM演算法 8 2.4 GHA與FCM於棘波分類之應用 9 第三章 棘波分類系統架構 10 3.1 GHA單元 10 3.2 FCM單元 20 3.3 Global控制器單元 27 3.4 FPGA-Based棘波分類系統 29 第四章 實驗數據與效能比較 30 4.1 開發平台與實驗環境 30 4.2 實驗數據呈現與討論 33 第五章 結論 46 參考文獻 48

    [1] M.S. Lewicki,“A review of methods for spike sorting: the detection and classifi-cation of neural action potentials,” Network Computer Neural System, Vol. 9, pp. R53R78, 1998.

    [2] S. Haykin, Neural Networks and Learning Machines, 3rd ed.; Pearson: Upper Saddle River, NJ, USA, 2009.

    [3] T.D. Sanger, “Optimal unsupervised learning in a single-layer linear feedforward neural network,” Neural Network, Vol. 12, pp.459-473, 1989.

    [4] Y. Sun, S. Huang, J. J. Oresko, and A. C. Cheng, “Programmable Neural Pro-cessing on a Smartdust for Brain-Computer Interfaces,” IEEE Trans. Biomedical Circuits and Systems, Vol. 4, pp.265-273, 2010.

    [5] T.-C. Chen, W. Liu and L.-G. Chen,“VLSI Architecture of Leading Eigenvector Generation for On-chip Principal Component Analysis Spike Sorting System,” Proc. 30th Annual International IEEE EMBS Conference Vancouver, British Co-lumbia, Canada, pp.3192-3195, 2008.

    [6] B. Yu, T. Mak, X. Li, F. Xia, A. Yakovlev, Y. Sun, C.-S. Poon,“A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis,” Proc. Interna-tional Conference on Field Programmable Logic and Applications, pp.556-561, 2010.

    [7] M. Aghagolzadeh, F. Zhang, and K. Oweiss,“An Implantable VLSI Architecture for Real Time Spike Sorting In Cortically Controlled Brain Machine Interfaces,” Proc. 32nd Annual International Conference of the IEEE EMBS Conference, Buenos Aires, Argentina, pp.1569-1572, 2010.

    [8] A. M. Kamboth, M. Raetz, K. G. Oweiss, and A. Mason, “Area-power efficient VLSI implementation of multichannel DWT for data compression in implantable neuroprosthetics,” IEEE Trans. Biomedical Circuits and Systems, Vol. 1, pp.128-135, 2007.

    [9] A. M. Kamboh, and A. J. Mason, “On-Chip Feature Extraction for Spike Sorting in High Density Implantable Neural Recording Systems,” Proc. IEEE Biomedical Circuits and Systems Conference, pp.13-16, 2010.

    [10] Y. Yang, and A. J. Mason,“On-Chip Spike Clustering & Classification using Self Organizing Map for Neural Recording Implants,” Proc. IEEE Biomedical Circuits and Systems Conference, pp.145-148, 2011.

    [11] S.-J. Lin, Y.-T. Hung, and W.-J. Hwang, “Efficient hardware architecture based on generalized Hebbian algorithm for texture classification,” Neurocomputing, pp.3248-3256, 2011.

    [12] N. Sudha, A.R. Mohan, P.K. Meher, “A self-configurable systolic architecture for face recognition system based on principal component neural network,” IEEE Trans. Circuits Syst. Video Technol, Vol. 21, pp.1071-1084, 2011.

    [13] S. -J. Lin, W. -J. Hwang, andW. -H. Lee, “FPGA Implementation of Generalized Hebbian Algorithm for Texture Classification,” Vol. 12, pp.6244-6268, Sensors, 2012.

    [14] J. Lazaro, J. Arias, J.L. Martin, C. Cuadrado, A. Astarloa, “Implementation of a modified fuzzy c-means clustering algorithm for realtime applications,” Micro-processor and Microsystems, Vol. 29, pp.375-380, 2005.

    [15] H. -Y. Li, W. -J. Hwang, and C. -Y. Chang, “Efficient Fuzzy C-Means Architec-ture for Image Segmentation, Sensors, Vol. 11, pp.6697-6718, 2011.

    [16] Y.-J. Yeh, H.-Y. Li, C.-Y. Yang, and W.-J. Hwang, ”Fast Fuzzy C-Means Cluster-ing Based on Low-Cost High-Performance VLSI Architecture in Reconfigurable Hardware,” pp.112-118, IEEE International Conference on Computational Sci-ence and Engineering, 2010.

    [17] L. S. Smith and N. Mtetwa, “A tool for synthesizing spike trains with realistic in-terference,” Vol. 159, pp.170-180, Journal of Neuroscience Methods, 2007.

    [18] Altera Corporation. NIOS II Processor Reference Handbook ver 10.0. 2010. Available online: http://www.altera.com/literature/lit-nio2.jsp (accessed on 3 May 2012).

    [19] Altera Corporation. SOPC Builder User Guide. 2011. Available online:http://www.altera.com/literature/lit-sop.jsp (accessed on 3 May 2012).

    [20] W. Reichert, “Indwelling neural implants: Stategies for contending with the in vivo environment,” in BMI-Related Thermal Studies. Boca Raton, FL: CRC, 2007.

    下載圖示
    QR CODE