以Sequence-Pair表示法處理植基於群聚策略之不確定模組平面規劃問題

隨著積體電路設計階層趨於複雜化，在後端實體設計(physical design)階段時才考慮電路模組平面規劃(floorplanning)問題已無法將規劃結果立即回饋予前端系統設計(system design)以便於修正其相對設計，因此我們考慮在前端系統設計階段模組尚未設計完成時即預先評估由這些不確定模組(uncertain modules)所形成的平面規劃結果，探討針對面積及維度大小不固定之模組如何進行未來平面規劃的評估。在本論文中我們提出一個植基於群聚(clustering)策略之不確定模組平面規劃演算法以便能有效的評估不確定模組所形成之晶片面積。在我們的方法中，給定每一個模組幾組不同的寬與高及其相對應之機率後，採用群聚技巧將模組聚集起來形成一些面積較大但個數較少的組合模組(supermodules)，接著以Sequence-Pair表示法來記錄組合模組間相對位置關係並在其上執行模擬退火(simulated annealing)程序以求得不確定模組所形成的最終晶片寬、高與其面積之機率分佈圖。

關鍵字

實體設計；平面規劃；不確定模組；模擬退火；群聚

並列摘要

As VLSI/SOC (very large scale integration/system on chip) technology advances, it is becoming increasingly inefficient for designers to feedback backend physical design floorplanning results to frontend phase for modifying the corresponding system design. Hence, it is important to consider evaluating floorplanning results during the frontend system design phase, which requires evaluating the chip area and dimensions by considering uncertain modules that have not been completely designed and have uncertain areas and dimensions. In this research, a non-slicing floorplanning algorithm based on a clustering strategy is proposed for effectively and efficiently evaluating the area of a chip of uncertain modules. In this method, when given certain sets of different widths, heights and corresponding feasible probabilities for each uncertain module, a clustering strategy is applied to grouping the modules for forming fewer supermodules of a larger size. Next, a Sequence-Pair representation for a non-slicing floorplan is used to record the relative positions among the supermodules; finally, a simulated annealing procedure is executed according to the Sequence-Pair representation for obtaining a better area distribution graph.

並列關鍵字

physical design ； floorplanning ； uncertain module ； simulated annealing ； clustering

國際替代計量

以Sequence-Pair表示法處理植基於群聚策略之不確定模組平面規劃問題

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